[SOLVED] Single Stage Logic gate meaning

[Arokia]

"In the next section NAND and NOR gates will be covered. (NAND are inverted AND gates) and (NORs inverted ORs gates). They both are single stage gates, and this is one reason why they are the basic blocks of CMOS logic."

Based on the above text, can anyone let me know what are single stage gates and why are they called so. And what would be a double stage gate.

Thanks,
Arokia

 

[d123]

Hi Arokia,

To be honest, I don't know. Perhaps logic like JK flip-flops would be a "double-stage gate" and that is why the text you reference refers to simple logic like and and or as "single-stage." As flip-flops can be made of multiple nand gates - "basic blocks of CMOS logic", maybe that is so.

Maybe it could be of help to other members answering you if you post a link to the page where this text appears, the name of the book and the page number, or to upload the pdf it comes from.

 

[ThisIsNotSam]

it's a terminology used for standard cells. "double-stage" gate is not really a terminology that is used, you would likely say multi stage. compare a flop to a NOR. think of the transistors in it and how they are arranged and how the diffusions are broken or continous. that is the notion of a stage.

 

[dick_freebird]

I have seen this called out pertaining to crystal oscillators.
Do not know why, but they worked better with very short
phase lag so there were specific CD4000 and 74HC inverter
types made with (drum roll...) one stage between input pad
and output pad.

It might also have had to do with less gain (or less squaring)
providing better spectral purity or lack of a tendency to jump
to 3rd overtone?

Now if you look at the structure and behavior of CMOS, you
can't get noninverting logic in one stage, you need logic
(inverting, as all CMOS stages are) and a second inversion
to make AND, OR etc.

 

[oratie]

Single stage - you can reach output pin from input only throuhg one transistor gate (don't care about source/drain). So, NAND/NOR/INV are si gle stage. AND/OR/BUF are double stage cells.

 

[dick_freebird]

Of course you may see in standard cell libraries
some variations such as nand2_1 being single
stage and nand2_2, nand2_3, ... being 3-stage
since getting good symmetric high drive from a
single stage gate's stacked (series) FET leg
becomes a real area hog.

 

[d123]

Of course you may see in standard cell libraries
some variations such as nand2_1 being single
stage and nand2_2, nand2_3, ... being 3-stage
since getting good symmetric high drive from a
single stage gate's stacked (series) FET leg
becomes a real area hog.

Hi,

Is what you describe the same as what this quote means in this forum (8th post down from top)?

The poster's statement is "The difference between 4069UB and 4049 is that the 4069UB has symmetrical output transistors and the 4049 does not." - I ask because it puzzled me looking at the respective datasheets and their schematic diagrams as to what the person meant.

I hope it's a fair question to throw into this thread by (hopefully) being directly related to the original question...