Single Sinus bursts generator needed

[aviaden]

Sinus bursts

hi,
I have a sinus generator around 650KHz, 5 vpp.

I need to produce a sin burst of exactly 1 cycle (at 650 HZ). The sin should start and end at exactly zero voltage.

The circuit should produce a single burst every time it is trigged.

I didn't manage to produce nice clean and precise bursts (because of timing inaccuracy...)

I'll appreciate any ideas on how to solve this problem.

Thanks, Aviad.

 

[FvM]

Sinus bursts

Did you use a zero-crossing detector?

 

[aviaden]

Re: Sinus bursts

Yes, I used a comperator for crossing detection. That gives me a clock (clk1) at the sin rate. But i need to synchronize this clock to another clock, clk2, that will determine the burst rate.

Lets say i need one burst every 1 msec, clk2 gives me a trigger every 1 msec. but i need to synchronize clk1 to clk 2 some how, so i'll get a nice sinus.

So that my problem.
Thanks, Aviad.

 

[FvM]

Sinus bursts

It seems to be a simple asynchronous logic (using e.g. two FFs and some gates).
Could be extended by a programmable cycle counter to generate a multi cycle burst.

 

[nashwan]

Re: Sinus bursts

hi
u can start with circuit like this . first stage is fast comparator as zero cross detector the output of that drive jonson counter (cd4017) the output of counter
drive analoge switch to capture sample
for ur project need
sample at 650hz u must use 3*(cd4017) to get divide 1000 .. R3&C1 drive
schmit trigger to get fine tune for output sample u can replace R3 with pot
to adjust start point of output signal ....U3A is CD4093
in this circuit output rate at 65khz add another (cd4017) to get 6.5khz and
another one to get 650hz

 

[FvM]

Sinus bursts

Yes, very good. I suspect however , that the burst enable is already switched "late" by 100 to 200 ns due to
various involved delays. So I wonder why you add an intentional delay. The burst trigger should be rather advanced, e.g.
by an adjustable comparator offset.

 

[nashwan]

Re: Sinus bursts

hi FVM
there is small delay time between cp0 and Q9 about 150ns i add that internaly
delay to capture the next cycle.

 

[FvM]

Re: Sinus bursts

i add that internaly delay to capture the next cycle

O.K., I see. But it wouldn't work with an only slightly varying frequency. So I think, fast logic (curiously, the comparator in your
circuit is faster than the digital logic, although it's actually the critical part) and a small phase "advance" at the comparator
would give a more stable result.

 

[nashwan]

Re: Sinus bursts

yes ur right.... but i suppose he use stable 650khz