single opamp compensation

[020170]

hi

last night I designed fully differential folded-cascode amp with Unit gain frequency 500Mhz

( 1p capacitor load )

but it have poor phase margin. so I think this circuit is needed to compensate.

but it's phase plot is so weird. and I don't understand how to compensate opamp.

In Edaboard, I found the pdf - book is labeled that "compensation tutorial"

but it is not practical. Is there anyone who have compensation tip or good E-book?

thanks.

**broken link removed**

 

[pseudockb]

Could you please post your schematic here as well?

 

[tsanlee]

There are dobule poles in you system. so you only have "NO" Phase Margin.

Do you need so large B.W. ?
The output impedance is so high ,here induce a pole.

 

[Vamsi Mocherla]

Importantly, is the Y-axis right? I mean you have a Y axis which calls of degrees. I do not think so. I do not think that there is an opamp which will cause a 5 degree phase shift.

Secondly, have you put the options as .OPTIONS UNWRAP for the phase plot? If you have done so, then the cause is due to two RHP zeroes and not multiple poles. The problem in the design could be due to the sizing of the cascode transistors which are at the current folding end. So, kindly verify them.

Also, have you used the positive input for testing the amp because there is no phase shift at DC. Are you doing a open loop test? If that is the case, you are actually looking for a lot of phase margin(which I think is next to impossible at those frequencies).

Kindly clarify me on these things.

 

[winsonpku]

Importantly, is the Y-axis right? I mean you have a Y axis which calls of degrees. I do not think so. I do not think that there is an opamp which will cause a 5 degree phase shift.

Secondly, have you put the options as .OPTIONS UNWRAP for the phase plot? If you have done so, then the cause is due to two RHP zeroes and not multiple poles. The problem in the design could be due to the sizing of the cascode transistors which are at the current folding end. So, kindly verify them.

Also, have you used the positive input for testing the amp because there is no phase shift at DC. Are you doing a open loop test? If that is the case, you are actually looking for a lot of phase margin(which I think is next to impossible at those frequencies).

Kindly clarify me on these things.

RHP zero/pole and LHP zero/pole have different effects on the circuit.
what is the difference?

 

[020170]

There are dobule poles in you system. so you only have "NO" Phase Margin.

Do you need so large B.W. ?
The output impedance is so high ,here induce a pole.

output impedance is low ,especially about 1.8K

 

[pseudockb]

The output impedance of a folded-cascode cannot be that low. Did you get your DC biasing correct?

 

[winsonpku]

There are dobule poles in you system. so you only have "NO" Phase Margin.

Do you need so large B.W. ?
The output impedance is so high ,here induce a pole.

output impedance is low ,especially about 1.8K

when you do the simulation,you must confirm that all the transistors work in the saturation regjion.if they all work properly,the output resistance can't be so small from my experience.

 

[020170]

all mosfet is under saturation.

in last I have a solution. everybody thanks.