sine wave does not generate output when there is another module in the simulator

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ruwan2

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Hi,

I use SMASH to learn verilog-AMS. I find that when I instantiate a sine wave generator only in SMASH, it can generate sine wave as I expect. When I add another module, no matter digital or analog, the sine wave output has only very small peak value noise (The names of sine module and amp module are different. Thus they are not shorted?).

Below is the head amp_out.pat file:



Here are sine and amp modules:



When I comment out

*.ELABORATE work.amp

it will have no sine wave in transient wave window.





I do not see restrictions on AMS LRM or SMASH reference book. What is wrong with my usage?


Thanks,
 

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