simultaneous use of rising and falling edge

[arshad_mir]

positive edge detector flilp flop

Hi,

I want to do some activity on both rising and falling edge of signal (say tick_ip) and do some other activity when there is no rising or falling edge



if (tick_ip ' event and tick_ip = '1')then
next_clockout<= '1';
else
next_clockout<= '0';

end if;

if (tick_ip ' event and tick_ip = '0')then
next_clockout_new<= '1';
else
next_clockout_new<= '0';

end if;

But the compiler is unable to synthesize it. Can anybody help me out

 

[nand_gates]

Do you want to use "tick_ip" as ur clock!
Then what ur trying to do is immpossible with current synthesis tools.
You should try doing some asynchronous digital
design which is not supported by current synthesis tools!
Hope you got my point

 

[arshad_mir]

In my earlier query, what I wanted to mention is:

if (tick_ip'event) then
clock_out <= '1';
else
clock_out <= '0';
end if;

I am not able to synthesize it.

 

[Black Jack]

In my earlier query, what I wanted to mention is:

if (tick_ip'event) then
clock_out <= '1';
else
clock_out <= '0';
end if;

I am not able to synthesize it.

You can synthesize this only for Xilinx CoolRunner II family.
They have dual-edge FF. For other familys/vendor this imposible this time, IMHO

 

[Renjith]

In my earlier query, what I wanted to mention is:

if (tick_ip'event) then
clock_out <= '1';
else
clock_out <= '0';
end if;

I am not able to synthesize it.

Hi arshad,
As mentioned by nand_gates u cannot synthesis this code at all.
Even if u target it to a a coolrunner II also, it won't work.
Bcoz when ever an event happens for the signal tick_ip, it is asked to stay HIGH.

can u plz explain what is that u r looking to ahcieve?

 

[Ace-X]

This is possible, but you have to divide it for 2 different processes. One process will be responsible for operations on rising edges. And second - for falling edge.

 

[r_e_m_y]

Hi arshad_mir,

Remember that what you write in vhdl describes logic elements or flip flop.
when you use my_signal'event argument, the sysnthesiser will always map my_signal on the clock input of a flilp flop (or inverted clock for falling edge ...).
What you seems to want to do is to detect a rising or a falling edge of a signal.
If your signal is slow and that you have a global clock signal in your design (for ex : signal at 1 Khz and clock at 10 MHz ...), you can do this for detection :

process (clk,reset_n)
begin
if reset_n = '0' then
signal_d <= '0';
elsif clk'event and clk = '1' then
signal_d <= signal;
if signal_d /= signal then -- edge detection
output <= '1';
else
output <= '0';
end if;
end if;
end process;

I hope this will help you.

 

[bibo1978]

I want also to note that not only coolrunnerII who have a dual clock FF, the Virtex-II, Spartan3, and Virtex-4 have a dual clock FF, which is the the DDR FF on the IOB.

 

[WA]

If you are using VHDL, I think this can't be done.
I'm using the @ltera board but, my text book and the board confirms this too.

The problem is you are trying to use the same signal twice.

example:
process (clock)
if (clock'event and clock = '1') -- rising edge
then ...
end if;
end process;

process (clock)
if (clock'event and clock = '0') -- falling edge
then ...
end if;
end process;

this code won't work because you can only use the clock in one process. so your compiller will generate some error, usually it will look at one only and disreguard the other process and not synthesize the second process.

trying to do it this way will fail also
example:
process (clock)
if (clock'event and clock = '1') -- rising edge
then ...
elsif (clock'event and clock = '0') --
then...
else
do nothing;
end if;
end process;

the problem is you can use the clock'event once. again the problem is the first event is the rising edge, but the compiler will complain about the second event.

maybe there is a way around this but, I haven't found one yet. I hope some member can and has found a way because, this would help me too.

Again this was using the byte blaster 2. I had a project to do in school (build a mini cpu) using VHDL and I had the same problems also.

My inputs to help and to further discussion.
wa

 

[Ace-X]

If you are using VHDL, I think this can't be done.
....
The problem is you are trying to use the same signal twice.

You are wrong. Also, if your textbook tell this - try to find better book.
You can check any signal any number of times in any number of processes.
So, you can write 10 processes, that have construction like "if (clk'event and clk='1') ..." and it will work.

Now, concerning your problem - I'm pretty sure this is because you are trying to assign to the same signal in different processes. This could lead to problems, because the same signal is forced by several drivers. Please, post here the whole code of your two processes (do not forget to use "code" tags to preserve formatting) and we will find the source of your problem.

As to using both edges of clock - as long as device has physical facility to use both clocks edges, it is possible.

 

[WA]

ace-x wrote

Now, concerning your problem - I'm pretty sure this is because you are trying to assign to the same signal in different processes. This could lead to problems, because the same signal is forced by several drivers.

I believe you have answered my question. The book I was using was Digital Design with CPLD Applications and VHDL by Dueck 2nd ed.
I was (at the time using my teachers copy 1st ed). Maybe I misread the chapter, but I remember reading about the clock event. It said you could use it only once?

I think I understand what you are saying here and it make sence.

I might have been doing it wrong (as this was my first attempt in VHDL). The problem here was that nobody else attempted VHDL here in school (except me) and the teacher thought It was great that somebody would try both VHDL and schematic entry.

I will say we were using the @ltera Max 2 plus board with Byteblaster 2. Could this have been my problem also.

The program is also in the second addition. Here is what the book is saying

--Illegal syntax (more then one clock per process)
PROCESS (clk)
Begin
    IF (clk'EVENT and clk = '1') THEN
        IF (load = '1') THEN
            q <= p;
        END IF;
    END IF;
    IF (clk'EVENT and clk = '1') THEN
        IF (count_ena = '1') THEN
            p <= q+1;
        END IF;
    END IF;
END PROCESS

The book says that one instance is allowed in a process statement. More then one instance implies more than one clock.
This what I was trying to say. I'm sorry if I caused any confusion.

But can I do this?

--Possible coding or will I have error message?
PROCESS (clk)
Begin
    IF (clk'EVENT and clk = '0') THEN
        IF (load = '1') THEN
            q <= p;
        END IF;
    ELSIF (clk'EVENT and clk = '1') THEN
        IF (count_ena = '1') THEN
            q <= q+1;
        END IF;
    ELSE
        q <= q; -- do nothing
    END IF;
END PROCESS;

I tried to follow above example for discussion and learning. Could this work?
I understand the compiler will complain about "Too Complex error" because I have tried to use more than 1 nested if statement.
Would something like this be too complex also?

Like I said I really couldn't talk to other class-mates because I was the only one doing this project. So help was non-existent. But I considered that project a wonderful learning experience and this topic also.

I hope this leads to more discussion as this will only help me in the future also.

Oh yes the project in school was from Mano's Third ed. Computer Architecture.
We used the 5th chapter to implement his mini-cpu. If you are familiar with this book, I think you can understand the problems I had doing this in both Schematic entry and VHDL only.

Thank you for your help and time
wa

 

[Ace-X]

Again, you have to use different processes if you want to use clock twice. In others words, in one process you are allowed to use only one if statement on clock. This is because VHDL construction like IF (clk'event and clk='1') is not analyzed/synthesized as logic construction by compiler - it is just recognized as prefix that the rest of process represents synchronous part. And because every flip-flop in FPGA/CPLD usually has only one clock input, therefore we can't make actions on both edges with the same FF (flip-flop), but we can make action with one FF on positive edge, with second on negative and then somehow join result on logic level. I hope, that corrections of your examples below will clear this.

Here are your examples re-written to follow described rules:

PROCESS (clk)
BEGIN
    IF (clk'EVENT and clk = '1') THEN
        IF (load = '1') THEN
            q <= p;
        END IF;
    END IF;
END PROCESS;
PROCESS(CLK)
BEGIN
   IF (clk'EVENT and clk = '1') THEN
        IF (count_ena = '1') THEN
            p <= q+1;
        END IF;
    END IF;
END PROCESS

PROCESS (clk)
BEGIN
    IF (clk'EVENT and clk = '0') THEN
        IF (load = '1') THEN
            q <= p;
        END IF;
    ELSIF (clk'EVENT and clk = '1') THEN
    ^^^^^^^
    you are trying to use clock twice inside the same process.
    even after you put these 2 IFs in different processes you have to
    make some re-coding, because your trying to drive the same signal 
    (signal q) in both processes. 
        IF (count_ena = '1') THEN
            q <= q+1;
        END IF;
    ELSE
        q <= q; -- do nothing
    END IF;
END PROCESS;

 

[Delsian]

You can use "NCLK <= NOT CLK;" and two "process(CLK)" and "process(NCLK)"

 

[crazy_man]

The best solution for this problem is to write three seperate processes - one dependent on rising edge, the other dependent on falling edge and the third one independent of that signal

 

[preet]

i am agree with crazyman, u have to use different processes.

 

[shakalaka]

hey all,
this may work...try this ...and let me know...
Process:1
begin
if (tick_ip'event) then
signal <= pre_Signal_state;
else
signal <= current_signal_state;
end if;
end process 1;

Process:2
begin
if (tick_ip'event and tip_ip ='0') then


end if



you can also try using state machine... that may also work