Simultaneous Read and Write in AHB

[fragnen]

Does Read and Write can happen simultaneously in AHB?

 

[FvM]

Seriously? AHB has WRITE signal determining transfer direction.

 

[fragnen]

Seriously? AHB has WRITE signal determining transfer direction.

Do you want to. mean that write and read cannot happen simultaneously in AHB?

 

[FvM]

How do you define simultaneous read and write? In AHB specification, HRDATA is shown to echo HWDATA at write cycle end. I won't consider this echo as simultaneous read write. Which AHB waveform do you expect for simultaneous read and write?

 

[fragnen]

How do you define simultaneous read and write?

By simultaneous READ and WRITE it is being indicated that Master can issue a READ and a WRITE transaction in the same clock cycle.

--- Updated Oct 20, 2023 ---

In AHB specification in the timing diagrams READ and WRITE waveforms are shown in the same diagram. From that it appears if it means simultaneous READ and WRITE is possible in AHB. Is that appearance correct?

 

[FvM]

As already stated, I see just a misunderstanding of AHB diagrams. Echo of write data has nothing to do with simultaneous read/write.

 

[fragnen]

As already stated, I see just a misunderstanding of AHB diagrams. Echo of write data has nothing to do with simultaneous read/write.

What do you mean you echo of write data? What did you mean by "HRDATA is shown to echo HWDATA at write cycle end"

Do you want to mean that write and read cannot happen simultaneously in AHB?