simulation- zero delay sim required if result is as expected per design?

[CVAGHASIYA]

hello, I am beginner

I have doubt that why do we need to do zero delay simulation ? even atpg tool generates pattern for design and we also improve the coverage. input pattern is generated and we also get the output pattern as per design. so that is expected output. so why it is necessary to do simulation as we get output as per design.

 

[barry]

How do you know you’re going to get the correct output if you don’t do a simulation?

 

[CVAGHASIYA]

How do you know you’re going to get the correct output if you don’t do a simulation?

okk...it means Atpg tool doesn't give correct output ???
please solve my doubt.

 

[kaz1]

functional simulation is needed to check your logic is doing what you intend. If you jump direct to timing simulation or hardware testing then by sheer great luck it may pass. If it doesn't not pass you need to see inside what is breaking.

 

[ThisIsNotSam]

okk...it means Atpg tool doesn't give correct output ???
please solve my doubt.

?
ATPG generates test patterns, period. It will succeed whether the chip/design has bugs or not.
Someone still has to do regular RTL simulation and that cannot be done via ATPG.

 

[dave_59]

okk...it means Atpg tool doesn't give correct output ???
please solve my doubt.

The purpose of ATPG is making sure the part that gets manufactured performs exactly the way the hardware description language code instructed it to be made. It tells you nothing about how well the code does to meet the requirements the part was supposed to satisfy.

This means if there are any mistakes in your design, ATPG proves that the manufactured part has the same mistake.

 

[song524]

Logic function has nothing to do with DFT
Simulation is to verify the function