Simulation with dynamic comparator problem

cmos dynamic comparators

HI! friends

I'm simulation with a dynamic comparator, but meet a problem i can't resolve it.
There are two simulation result, fig 1 is my simulation result, fig 2 is i want to get result.

The simuation parameter are following
Vref+ =Vref1 =1.9V
Vref- =Vref2 =1.1V
Vin+ =Vin1 =DC 1.5V ,5MHz
Vin- =Vin2 =1.3V
VDD=3V
The comparator threshold leve are 0.2V and 0.4V
Result represent by (Vout+) - (Vout-)

I don't know how to resolve this problem anybody can help me, please.
Sorry!my English is poor
Thanks for your help

Well, to start the comparator schematic is wrong: you should apply Vin+/Vref+ to one differential pair and Vin-/Vref- to the other one.

Then, your input must be differential (it seems to me that your Vin- is fixed and that is NOT the idea).

Rgds

maxwellequ said:

Well, to start the comparator schematic is wrong: you should apply Vin+/Vref+ to one differential pair and Vin-/Vref- to the other one.

Then, your input must be differential (it seems to me that your Vin- is fixed and that is NOT the idea).

Rgds

Click to expand...

Hi.
first of all this schematic is completely right. Actually I think it's the exact picture from Sumanen Thesis, they call it "Differential Pair Comparator". Am I right leokaven? And this circuit became a paper

L. Sumanen, M. Waltari, K. Halonen, “A Mismatch Insensitive CMOS Dynamic
Comparator for Pipeline A/D Converters,” in Proceedings of the IEEE International
Conference on Circuits and Systems (ICECS’00), Dec. 2000, pp. I-32–35.

But a better and more complete paper would be

L. Sumanen, M.Waltari, K. Halonen, “CMOS Dynamic Comparators for Pipeline
A/D Converters,” in Proceedings of the IEEE Int. Symposium on Circuits and
Systems (ISCAS’02), May 2002, pp. V-157–160.

And why you can't get a right output? As I remember this circuit have a complex equation to set its trip point. Maybe you didn't make it right. Besides, to make sure your circuit works properly a better test input would be a ramp which can be produced by PWL instruction in HSpice. This ramp will start from 0 to Vdd. When it crosses the trip point and be larger than that the output will be high and vice versa. Sometimes a problem like yours may occur because of not a suitable CM level. you can change your input CM levels to 1.6 for Vin+ and 1.4 for Vin-.

Good luck.
Regards,
EZT

Dear ezt,

In fact this seems the Fig. 4.2 of Sumanen's Thesis. But I mantain what I said: THIS IS WRONG.

If (VREF+)-(VREF-) is larger than sqrt(2).Vovd (input saturation voltage of a diff pair), one of the transistors in the differential pair, the tail current flows entirelly in one of the transistors -> circuit becomes insensitive to the values of the VREFs. Therefore this circuit only works if Vref+ is not very far from Vref- (which does not seem to be the case)

See, for example:
Y. Wang and B. Razavi, "An 8-bit 150-MHz CMOS A/D Converter", JSSC, pp. 308-317, March 2000 (Fig. 12)

Rgds

Dear maxwellequ,

So long as the diff pair of vref doesnt go out of the linearity region, the structure will be ok.

Design techniques for high-speed, high-resolution comparators