ijy
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I am taking a course on digital design as part of my undergrad, and I am stuck on a homework problem. One part of the problem asks "explain how one should choose the simulation step size, if one does not just use a default value provided by the simulator."
I cannot find any mention of this in my digital design textbooks, the VHDL-2008 standard, or any search engine results. Can anyone tell me how the minimum simulation step size is determined and if a designer can have control over this value?
I read on a separate thread that the simulation can be either "event" simulation or "cycle" simulation. I am assuming that cycle simulation means the simulation step size is equal to 1/2 the clock rate. Would this then be the smallest useful step size?
I cannot find any mention of this in my digital design textbooks, the VHDL-2008 standard, or any search engine results. Can anyone tell me how the minimum simulation step size is determined and if a designer can have control over this value?
I read on a separate thread that the simulation can be either "event" simulation or "cycle" simulation. I am assuming that cycle simulation means the simulation step size is equal to 1/2 the clock rate. Would this then be the smallest useful step size?
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