katrin
Full Member level 1
I am doing some simulations of two multistage CMOS current mirrors including PMOS and NMOS current mirrors.
In principle, their output currents should be the same when the current sources and the amplification factors are the same
But in fact, the output currents of these two multistage CMOS current mirrors have 2% different in the schematic simulation.
I am confused about that. Even if the mismatching problem exits, it should only show up in the post-sim including layout, but not in this schematic simulation.
In principle, their output currents should be the same when the current sources and the amplification factors are the same
But in fact, the output currents of these two multistage CMOS current mirrors have 2% different in the schematic simulation.
I am confused about that. Even if the mismatching problem exits, it should only show up in the post-sim including layout, but not in this schematic simulation.