Simulation problem with TRAN analysis as output oscillates

[tyanata]

Hi,

I design reference voltage source. I have following problem when I simulate Power suuply dependence, if I use DC analysis it's allright, but if I use TRAN analysis, the output of the cicuit oscilates.
Can anyone give me advice.

 

[sunking]

simulation problem

try ac anaysis

 

[scottieman]

Re: simulation problem

Hi,

I design reference voltage source. I have following problem when I simulate Power suuply dependence, if I use DC analysis it's allright, but if I use TRAN analysis, the output of the cicuit oscilates.
Can anyone give me advice.

it means your bandgap is unstable.
What kind of topology you are using?
If you are using the CMOS one with amplifier as a clamping element, you are required to do frequency compensation. The simplest way is dominant-pole compensation, putting a large capacitor at the output of the error-amplifier.

Scottie

 

[tyanata]

Re: simulation problem

That is the circuit wich I design.

Qext and Rext are extenal components.
Vin is between 8 and 16V.
Vout is about 5V. There is a simulation load at Vout node 5K ( I(Vout)=1mA)

V1 is about 4.6V.
V2 is about 5.7V.

 

[Humungus]

Re: simulation problem

Justy one question; shouldn't the bipolars be NPN? In the case shown, PNP, each current source made of MOS, has a smaller Vds than the precedent, so that current matching is really ugly!!!

Concerning your oscillation, I think that you should guarantee a minimum output current and then maybe put a capacitor on the base of the output transistor.

 

[tyanata]

Re: simulation problem

Tranzistors Q1, Q2 and Q3 are PNP, (in our CMOS process, trere aren't NPN tranzistors.

I have tried with capacitror at the base of Qext- it doesn't help.

Added after 20 minutes:

There is another effect if the simulation is 0.35ms there are oscilations, but if simulation is 35ms there aren't oscilations and Vout=5.

If the simulation is 0.35ms, in the beginning Vin= 0 in 0.1ms Vin starts to increase, in 0.2ms Vin=16V

If the simulation is 35ms, in the beginning Vin= 0 in 10ms Vin starts to increase, in 20ms Vin=16V.

 

[marshel]

simulation problem

I think maybe you can add a cap in v1 node.
by the way, what about the ibias current and R1 value and the osc freq?

 

[tyanata]

Re: simulation problem

It is interesting that all the circuit oscilates. There are oscilations at every node in the circuit.

This is the bias circuit: M1, M2, M3, M4 and Rbias. M1 and M2 are deep in strong inversion, M3 and M4 are at border between strong inversion and weak inversion. M5,M6 and M7 are start-up circuit.

 

[Humungus]

Re: simulation problem

Just one more thing. Remove Qext and the diodes, and see if the reference oscillates. If it does, then concentrate to sbilize the reference and then proceed to analize the whole circuit.

It is normal that you found the oscillation when simlulating 0.35ms while the circuit does not oscillatoe when simualting 35ms. When simulating 0.35ms, the time step is smaller, then the simulator can see thinner detail.

But, to really check that the circuit is unstable (actually it is it), you must perform AC simulations and stabilize every loop.

 

[tyanata]

Re: simulation problem

I know how to do AC analysis of operatinal amplifier, and how to compensate it.
But in this is circuit can you give me advice or (paper) how to perform AC analysis, and how to compensate circuit.

 

[Humungus]

Re: simulation problem

Remove first Qext and diodes. Open the gate of M5 and place here the AC source. Place big inductors (10e10) and capacitors (10e10) in order to bias your circuit and at the same time to decouple any AC feedback as shown. The replica amplifier is to load the main amplifier as in the actual case. Look for yours output signals ath the output of main amplifier.