Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Simulation of the ideal DAC in Cadence

Status
Not open for further replies.
M

moisiad

Member level 4
Member level 4
Joined
Mar 31, 2004
Messages
71
Helped
2
Reputation
4
Reaction score
1
Trophy points
1,288
Location
GREECE
Activity points
719
Hi

I am simulating in Spectre the ideal 8bit DAC from the AhdlLib. What seems strange is that from the DFT analysis the SFDR is about 60db. It is to small for the ideal case. Have you ever come up with this case?

Thanks
 

how much is the idea?
be careful that it is only 8 bit.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top