omidsht
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modelsim error
Hi ,
when i simulate my source vhdl code withoutr sunthesis(functional simulation) every thing is okay . but after i synthesize my vhdl code with ISE 9.2 or 10.1 , i create the post synthesis model and post place and route model for simulation , then when i want to simulate these models with modelsim6.4c , after about 2000 ns of simulation it stops and says : error : the simulation time limit reached , note: delays were truncated !
what shall i do ?
thanks in advanced.
Hi ,
when i simulate my source vhdl code withoutr sunthesis(functional simulation) every thing is okay . but after i synthesize my vhdl code with ISE 9.2 or 10.1 , i create the post synthesis model and post place and route model for simulation , then when i want to simulate these models with modelsim6.4c , after about 2000 ns of simulation it stops and says : error : the simulation time limit reached , note: delays were truncated !
what shall i do ?
thanks in advanced.