we tried simulating an I2C verilog code in Xilinx. But then, it seems that the output waveform is not good. we really need help in understanding what's wrong with the simulation/output waveform. I attached the code and the waveform is shown below:
That's a lot of X's. Are you sure that all registers get a valid value at the start of the simulation?
I notice the rstn being asserted (going low) a very short time, but that looks a bit too optimisitc. How about asserting the reset during the first 100 ns, and see if that helps any.
Judging by the screenshot, that is not what you did though... In the screenshot the "rstn" is low for half a clock cycle just like before. Only now you do the assertion around t=100ns.
For a reset that is asserted from t=0ns to t=100ns, you need something like:
Code:
initial begin
rstn = 1'b0; // assert active low reset
#100
rstn = 1'b1; // de-assert active low reset
end
Note that for the sake of simplicity I assume you use the default timescale in ISIM (1 ns).
Also make sure that you use the proper reset polarity, in case you use other people's modules. A lot of xilinx stuff uses active high resets.