Simulation of I2C in Xilinx

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daisyzari

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we tried simulating an I2C verilog code in Xilinx. But then, it seems that the output waveform is not good. we really need help in understanding what's wrong with the simulation/output waveform. I attached the code and the waveform is shown below:



Thank you
 

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  • i2c_verilog.zip
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That's a lot of X's. Are you sure that all registers get a valid value at the start of the simulation?

I notice the rstn being asserted (going low) a very short time, but that looks a bit too optimisitc. How about asserting the reset during the first 100 ns, and see if that helps any.
 

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mrflibble,
I tried asserting the reset for the first 100ns and this is what we got:



Thank you so much for the help
 

I tried asserting the reset for the first 100ns ...

Judging by the screenshot, that is not what you did though... In the screenshot the "rstn" is low for half a clock cycle just like before. Only now you do the assertion around t=100ns.

For a reset that is asserted from t=0ns to t=100ns, you need something like:

Code:
initial begin
    rstn = 1'b0; // assert active low reset
    #100
    rstn = 1'b1; // de-assert active low reset
end

Note that for the sake of simplicity I assume you use the default timescale in ISIM (1 ns).

Also make sure that you use the proper reset polarity, in case you use other people's modules. A lot of xilinx stuff uses active high resets.
 
Last edited:

Umm.. but that's what we did or maybe we forgot to save it.. we'll check again.. thanks..

---------- Post added at 13:48 ---------- Previous post was at 13:42 ----------

This is what we did..

Code:
	initial
	  begin
                     rstn = 1'b1; // negate reset
	      #100;
	      rstn = 1'b0; // assert reset
	      repeat(1) @(posedge clk);
	      rstn = 1'b1; // negate reset
                   end

is this correct?
 

is this correct?

No. It does explains how you got the signal in the screenshot though... Anyway, I suggest you try my previous suggestion.
 

Did you get things working now?
 

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