Simulation Mismatch between systhesis results in Design compiler

[ahmad898]

I have synthesized a design using Synopsys DC and I checked the post-synthesis simulation results. When using Compile ultra option in DC, the pre-synthesis and post-synthesis simulation is completely matched, albeit at the expense of the gate delays. However, when I use the simple Compile option, there is a mismatch between pre and post-systhesis results.

My question is, what is the origin of such mismatches between compile ultra and compile in DC.
Please note that the designs do not have any timing error, timing loops, or unwanted latches in any of the cases.

 

[ThisIsNotSam]

the compile and compile_ultra commands are very similar. compila_ultra has a specific recipe of what optimizations to enable while the compile command gives you freedom to pick them almost one by one. I cannot think of any reason why compile would generate a netlist that does no match.

I would recommend for you to run LEC on the two netlists. gate-level simulation has a lot of caveats, you might stumble on some poorly defined library condition, lack of SDF, lack of this, lack of that, some default flag enabled. bad testbench. all sorts of things can be leading you to believe the netlists are different. if you can, run LEC, then come back here and let us know the result.

 

[ahmad898]

I use LEC on the two netlist and they are matched. It seems the testbench has some problem. Thank you for your suggestion.

 

[dick_freebird]

Transistor netlist will match regardless of routing, but parasitic burdens vary in size and distribution as you vary the route-to constraints. perhaps your "simple" config "lets things (i.e. detail timing) slide" to the point that this affects outcomes.

My first concern in such a situation would be that a low speed functional, at-speed marginal routing is what's been made (this can pass many checks). Try best and worst timing corners to expose that, by any difference in results (when strobed such that, generally, things line up).

 

[ThisIsNotSam]

Transistor netlist will match regardless of routing, but parasitic burdens vary in size and distribution as you vary the route-to constraints. perhaps your "simple" config "lets things (i.e. detail timing) slide" to the point that this affects outcomes.

My first concern in such a situation would be that a low speed functional, at-speed marginal routing is what's been made (this can pass many checks). Try best and worst timing corners to expose that, by any difference in results (when strobed such that, generally, things line up).

there is no routing involved at this point. there were two netlists coming straight from logic synthesis with a mismatch in simulation. the mismatch must come from somewhere else.

 

[dick_freebird]

If your synthesis is allowed to mess with buffer trees and such, for anticipated wireless and fanout,same deal.

If you don't enforce identical goals, methods & constraints then identical results can't be expected (other than luck)?

 

[ThisIsNotSam]

If your synthesis is allowed to mess with buffer trees and such, for anticipated wireless and fanout,same deal.

If you don't enforce identical goals, methods & constraints then identical results can't be expected (other than luck)?

you absolutely 100% expect results from logic synthesis to match. both in LEC and in gate level sim. if they don't, it is a huge red flag.

 

[rca]

as rise by ThisIsNotSam, LEC is here to validate the netlist post synthesis is identical to the RTL, never rely only on the TB.

Both post synthesis netlist (with any option if both RTL are identical) must be LEC, if not, contact Synopsys.