Simulation in DFT

[Mak444]

What is the need of doing no-timing simulation? As during ATPG the tool has already done simulation and generated simulated patterns. What is the difference between the simulation done by ATPG and that done by vcs (Gate Level Simulation)?

 

[glennramalho]

The idea is to make sure it is all working. Yes, the DFT tool (Tetramax, Modus, Tessent) did do an internal analysis so it is likely to work, but it is often best to double check the results. Some chips also may have a complicated sequence to enter ATPG mode or perhaps need a certain pattern on the analog side, and these are beyond the scope of the DFT tool. So the simulation is to make sure it will work.

Your DFT tool does do something like simulation it might not have all the parameters that your simulation will have like analog models, IP models, and maybe some analog pin combination.