[SOLVED] Simulating the input capacitance of digital instance

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Junus2012

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Hello,

I need to simulate the input capacitor of a CMOS gates. Particularly now I am interested to see the input capacitance at the clk input of the D-flip flop. Knowing this value will help me to estimate the loading effect on the clock source and so the clock source fanout.

Thank you

Regards
 

Use a vpulse with a finite, technology-appropriate rise
and fall time, plot the current, C=I/(dV/dt) which you
know from setting it.
 
Dear friends,

Thank you for your reply,

after looking to the discussion between simulating the input capacitance from ac or transient I saw that people went in favour of ac one as also suggested by Pancho,

Could you please put me in more details of the simulation setup, and please excuse my poor knowledge.

I will take the example of finding the input capacitance by the clock input of the D-flipp flop. I am thinking to connect the clock with logic high voltage (3.3 V in my used technology), in series I connect an ac source with mag =1 then I run the AC simulation. I have to plot the current I in the clock terminal, based on this current I can find the input capacitance as expressed as

Cin_diff=imag(Yin_diff)/(2*pi*freq)

Please confirm me my test so I can update the post by the result

Thank you once again
 

Junus2012 said:
I am thinking to connect the clock with logic high voltage (3.3 V in my used technology), in series I connect an ac source with mag =1 then I run the AC simulation.
Click to expand...
Transient signal has no meaning in AC analysis.

I assume you use Cadence Spectre.

If you would like to evaluate AC capacitance at specific time point, use transient analysis with setting acnames and actimes or use PSS/sampled-PAC.

See "spectre -h tran" and "spectre -h pac".
 

Dear Pancho,

Yes I am using the Spectre,

I don't want to simulate the capacitance for a specific time, rather than simply the input capacitance
 

Assume rectangular pulse as clock.
Cin is different for low level, high level, rising edge and falling edge.

What Cin do you want to evaluate ?

Average Cin over one period of clock ?
Or simply Cin for static DC input level ?
 
pancho_hideboo said:
Assume rectangular pulse as clock.
Cin is different for low level, high level, rising edge and falling edge.

What Cin do you want to evaluate ?

Average Cin over one period of clock ?
Or simply Cin for static DC input level ?
Click to expand...

Thank you Pancho for your reply,

I think logically for digital circuit running with clock, then "Average Cin" should be extracted to be considered as equivalent input capacitance, So yes I am interested in simulating the Average Cin
 

To get an average Cin by AC small signal means, you
would want to perform the analysis at multiple points
across the signal range. Some technologies will show
very different Cgg at different bias-points (FDSOI, for
example, has no gate depletion capacitance to speak
of, when "Off", only the Cgd+Cgs overlap, while "on"
devices have this plus W*L*Cox. So you may see a
compound CV curve that has low Cin within VT of
either rail, fattening up in the midrange.

Point being, you ought to not just believe a Cin number
at Vin=Vdd/2 or whatever, is "the average".

I am fine with small signal analysis for small signal
operation if it's the application reality. But bang bang
digital is large signal discrete time, and I like to use
a corresponding analysis and "see what I see" with
fewer surprises / rosy assumptions.
 
Dear friends

I took time to try the simulation using PSS/PAC but unfortunately I couldn't success to understand these simulation and never worked with it beofre,

Therefore I switched to the traditional method based on applying a Voltage clock and measuring the current, then as freebird suggested from the general capacitor formula I found Cin=i/(dv/dt). Results are attached below, as well as the circuit.

I am getting Cin=3.5 fF, which I believe in my opinion is very less to have from CMOS circuit, isn't it ? I would usually expect at least several tens or hundreds fF.
Then I tried to check if something wrong with this method, so I connected a clock on a pure 1 PF capacitor and the setup was right, I got also 1 PF from the simulation means the idea is ok.





Thank you in advance
 

As a sanity check you could look at the .OP results for the two
transistors of the logic input, see what Cgs, Cgd, Cgb roll up to.
Maybe run low, high and vdd/2 positions just for coverage.
 
I have just did another test to verify this setup, I connected a big capacitor of 1 pF at the clock input which should dominate the input capacitor if it was really in fF, and the result agreeing with the setup, I am getting by the simulation Cin =1.003 pF

- - - Updated - - -

dick_freebird said:
As a sanity check you could look at the .OP results for the two
transistors of the logic input, see what Cgs, Cgd, Cgb roll up to.
Maybe run low, high and vdd/2 positions just for coverage.
Click to expand...

Dear free_Bird

I have followed your idea by recording the capacitor from operating points at different levels of the clock signal, so I connected DC source at clock with V=0, then V=VDD*0.5, and V=VDD. The attached images are representing the values for the input and pmos transistors at the clock, I also attached these two transistors,

The circuit is looking for me something strange, I am using the DFF from Austriamicrosystems,









As you see from the results that cgs or what ever are in fF or less
 

So by transient method you have 3.5fF, while individual
transistors show "cgg" in the 0.4 - 1.4fF range apiece.
So right order of magnitude at least.

1pF would be on the order of a chip input pin, post, wire,
pad, ESD network and the active buffer front end. The
active buffer probably being the least of these, although
sometimes people will design the buffers with large devices
as the input drive is "free" and high fanout capability is
a good thing, as a rule.

This is far from being similar to a core logic inverter.
 

Thank you free_bird

Your method is working perfectly and it is simple to use,

Indeed you answered other part of my coming questin, if the input cap of this flisp is like this very small then I should not think about buffering the clock, because the input buffer capacitance might be in this order or even higher, I should only consider designing the buffer if for example I am going to connect large number of this DFF or as you said for the case of the chip input pin

Thank you once again
 

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