Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Totally inappropriate tool for the task. Unless you mean circuit simulation of the process, macro model style.
If you mean to arrive at an expected write time by simulation I think you're out of luck. Oxide drift and damage are still something you "back into from data to fit" last I talked to TCAD peeps who'd know.
So if it's circuit then you want that data to fit mechanism and outcome of your gate-zap model. Get data on limiting resistance dimension as well as voltage & time. If a prescribed programming method is called out, learn to emulate it (as seen by the zap element t=0 and as it evolves; an element that has a self limiting region must be hit hard (adiabatic) or get an unknown-quality, -reliability bit.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.