Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

simulating substrate noise in mixed ic with cadence

Status
Not open for further replies.
T

tavakoli

Member level 3
Member level 3
Joined
Dec 31, 2003
Messages
66
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,286
Activity points
669
does Cadence support simulating Substrate Noise in mixed ics (like clock noise and etc) with extracing noise models and noise coupling from layout of a design?????
 

Cadence has a special tool -- SNA (substrate noise analysis) can do that.
 

what versions of cadence have that tool?
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top