Simulate the offset of a Switched amplifier

[AMSA84]

Hi guys,

How can I measure the offset of a switching amplifier?

Regards.

 

[KlausST]

Hi,

What is a switching amplifier? Do you mean a Class D audio amplifier?
What offset? Offset voltage? At input or at output or somewhere else?

Schematic, please, and device type.
Please give detailed informations.


Klaus

 

[Vbase]

Switching amplifier has a 0V offset. You can still measure the offset by shorting the input to ground and divide the output by the gain, the same way as any other amplifier.
The idea of these amplifiers is switching the input from ground to input voltage and subtracting the two outputs with differential amp, this cancels out the offset voltage of the amplifier because both outputs contain the same offset voltage multiplied by the gain.

 

[dick_freebird]

You would be best off to run a transient analysis (with the
tolerances set adequately to get better simulation accuracy
than what you seek to measure) that runs across multiple
cycles in an application-realistic way.

You should build in, or take advantage of, device-level
mismatch statistics or worst-casing, if you want to test
the robustness of any auto-zero function (if it's that kind
of amplifier, and not a Class D).

Class D audio doesn't care much about DC offsets, I think.
0Hz is out-of-band.

 

[AMSA84]

Hi guys,

Sorry for the little information I gave.

So it's an autozeroing amplifier, tehc 0.13u, using the principle of operation that we can find in razavi's book. The topology is a two-stage opamp with an aux amplifier.

Vbase a switching amplifier doesn't have 0V offset. That's impossible. How would you measure that offset? I put the amplifier in a buffer condition and I did the simulation. I don't know if this is the correct way to do it. By the way, something wrong is happening. The offset in typical operation has tens of uV but when performing MC it jumps to mV. Any suggestions of what might be causing this?

 

[dick_freebird]

Natural mismatch ought to be in the tens of mV, FET:FET. Autozero
takes out some portion of the lineup mismatch rollup; the back end
offsets are only divided by front end gain, so some residue ought to
be seen.

If you are able to run a single MC iteration (look at the Vio result
and find the worst case iteration, and rerun that "standalone" with
MC functionality enabled) then you could debug the "bad actor".

This could be a circuit problem, some devices not being corrected.
It could also be insane statistics, which of course your CAD folks
will never admit to, but you could prove if you dug deep enough.
If (say) you found one transistor whose .OP VT was 100mV out
from the rest, you might call it a "point defect" rather than a
normal mismatch and negotiate it away, at design review, on that
basis. Been down that road once or twice, models are not to be
blindly accepted (especially when everybody has piled on their own
statistical sandbagging with no thought to the rollup result, vs fab
capability).

 

[AMSA84]

Hi dick,

Thanks for you reply.

Can you explain a bit more about your suggestion of running one MC iteration? Didn't understand. How can I simulate the stand alone with MC? What's the vio?

Taking the advantage of this post, allow me to ask you the following. Is it possible to have single output autozeroing amplifier using an auxiliary amplifier? For example the 2stage opamp and an auxiliar stage like in razavi?

Regards.

- - - Updated - - -

Are you referring to the sensitivity analysis?

 

[dick_freebird]

I don't know your tool-set. But "back in the day" using Spectre MC,
you could get to any MC iteration number by setting certain Monte
Carlo mode / enable flag variables (process and mismatch) and set
mccnt=X (the iteration of interest). Run just that one, and you can
probe / print / plot anything (unlike MC loop where you only get the
saved Calculator or selected print results). You can debug your Vio
(input offset voltage) then, as you would any normal non-MC
simulation.

Autozero amp could be doable, but you'd need to adapt the feedback
perhaps, and ensure that front end gain (in the zeroing portion) can
squelch any backend / single-ended offset that's causing an input
referred offset. And there's a limit to how much front end gain you
can have and still zero it. So you might look first at the back end
and see if it's in fact the problem (like needing the zeroed part to
travel to a place where it's operating unlike its zero-point, near one
rail or the other, etc. in order for the output to reach its closed
feedback point).

 

[AMSA84]

Good point. But how the heck I do that in Cadence 6.1?

 

[AMSA84]

UPDATE:

I think I found it dick. Thanks. Excellent suggestion and I think why the cricuit was behaving like that. But need a bit more investigation.

 

[AMSA84]

Guys, one question please:

Like you know I am trying to simulate the offset cancellation circuit in razavi's book.

This is the circuit:



I would like to ask you guys first if you think the circuit is correct? I did a small change, passing it from differential to single ended. Is that correct?

Then, to measure the offset, I doing the connections that you guys can see in the picture and taking the difference between point 5 an point 2 as well as point 1 and point 2.

Now, both of them gives different values. The first option, point 5 to 2, gives me a square wave with something around 1.8V while the other one gives me 300uV. Square wave as well.. So I am confused. Which one is the correct way to measure the offset??

Regards.

 

[AMSA84]

Anyone please?