Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Simulate channel loss

L

LiaoJJ

Newbie
Joined
Apr 28, 2024
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
33
Hi,

I'm now studying clock and data recovery circuit, I have been used verilog-a to generate prbs7 signal with SSC. I want to simulate -3dB loss for channel loss.
Do anyone have some idea?
I tried to export the signal to .txt from waveform in hspice, and then simulate the transmission line in Matlab Simulink, finally get the attenuated signal and import to hspice.
But I have no idea how to do?

Thanks for any help
 

LaTeX Commands Quick-Menu:

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top