Simple Xilinx ISE Error - Xst:647 - Input <Qin> is never used.

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Knoxort

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I keep getting this error whenever I try to synthesize.

WARNING:Xst:647 - Input <Qin> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

The thing that really drives me around the bend is that the declaration for Q mimics A perfectly, as they essentially have the same basic function, just for grabbing their inputs. I don't understand why I get a warning on Q but not A. Any suggestions? Below is a relavent snippet of the code, with A and Q highligted

Code: 
entity Shift_and_Add_Unit is
    Port ( [B]Ain  : in  STD_LOGIC_VECTOR (15 downto 0);
           Qin  : in  STD_LOGIC_VECTOR (15 downto 0);[/B]
			  M    : in  STD_LOGIC_VECTOR (15 downto 0);
           CLK  : in  STD_LOGIC;
           Aout : OUT  STD_LOGIC_VECTOR (15 downto 0);
			  Qout : out  STD_LOGIC_VECTOR (15 downto 0));
end Shift_and_Add_Unit;

architecture Behavioral of Shift_and_Add_Unit is

[B]SIGNAL A : STD_LOGIC_VECTOR( 15 DOWNTO 0 );
SIGNAL Q : STD_LOGIC_VECTOR( 15 DOWNTO 0 );[/B]
SIGNAL C : STD_LOGIC := '0';
SIGNAL temp_sum : STD_LOGIC_VECTOR(15 DOWNTO 0);

--SIGNAL shift_temp : STD_LOGIC_VECTOR( 15 DOWNTO 0) := "0000000000000000";


begin

PROCESS (CLK)

BEGIN

IF RISING_EDGE(CLK) THEN


[B]A(15 DOWNTO 0) <= Ain(15 DOWNTO 0);

Q(15 DOWNTO 0) <= Qin(15 DOWNTO 0);[/B]

--IF (Q(0) = '1') THEN
		
		--temp_sum <= A + M;
		--A <= temp_sum(15 DOWNTO 0);
	
	--END IF;
	
	--For now, ignoring carry
	
	Q(14 DOWNTO 0) <= Q(15 DOWNTO 1);
	
	Q(15) <= A(0);

--	A(14 DOWNTO 0) <= A(15 DOWNTO 1);
	
	A(15) <= C;
	
--	shift_temp(15) <= A(0);
--	shift_temp(14 DOWNTO 0) <= Q(15 DOWNTO 1);
--	
--	Q <= shift_temp;
--	
--	shift_temp(14 DOWNTO 0) <= A(15 DOWNTO 1);
--	
--	A <= shift_temp;

END IF;

[B]Aout <= A;
Qout <= Q;[/B]


END PROCESS;
 
Last edited by a moderator:

According to your code, Qin is unused. This assignment:

Q(14 downto 0) <= Q(15 downto 0);
Q(15) <= A(0)

Overrides the previous assignment:

Q <= Qin;

In a process, it is the final assignment that gets taken.

You should also note that Ain(15) is also unconnected (for the same reasons)

Also: when you post code, please do not post code that is commented out - it makes it harder to read (it is also bad practice to leave code commented out). Also, use code or syntax tags in your posts.
 

Thanks a lot. I switched to variables, so all assignments would be read. I'll remember what you said about formatting; sorry about that.
 

What have you switch to variables? does it create the correct hardware? I fear you're just changing it without understanding what the consequences are.
 
Well, I was using the signals inside a process; My basic ideas was to preform some simple manipulations on the input signals (addition, shifting, etc.) within the process in order to obtain outputs. Variables should be used in this situation, correct? Signals wouldn't update until the end of the process, which would be a problem for me.
 

There is no reason to use variables. Everything you can do with variables, you can do with signals. You need to forget about how the code works and think about how the hardware should work. And as a beginner I recommend never using variables. They can cause you problems.

What is your desired hardware? have you drawn the circuit out on paper before you wrote any VHDL?
 

The basic goal of the project is to build a pipelined version of a shift and add multiplier. The specifications were to multiply 16 bit numbers and obtain a 32 bit product. I did this by creating a basic core process that accepts two 16 bit binary numbers and shifts them. It also adds to a running sum if the lowest bit of one, the shifted multiplier, is a one. It is meant to emulate the partial product method of multiplying. I used variables in the process because I needed them to change instantaneously. From there, I strung connected 16 of these in series, for the 16 times this operation would have to be done.

It seems to simulate well behaviorally, but not in the post place and route model. Also, I've only tested using a steady multiplicand and multiplier, as opposed the varying inputs my professor wants, to make it a true pipeline design.

I didn't draw out a circuit because it seemed less helpful for this kind of design, although I'm regretting that a bit now. With using signals as opposed to variables, would I have end up using more numerous, but discrete and specific hardware blocks?
 

Variables and signals can produce the same hardware - it depends how you use them. But signals will be more consistant in their behaviour, and there is almost nothing you can do with variables you can also do with signals (in terms of RTL description). So as a beginner, you should get used to ALWAYS using signals. If you think you need a variable, you're probably lapsing back into C mentality.

I suggest drawing the diagrams out - it will help you with your RTL description as you should be able to map each peice to RTL code directly.
 

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