simple calculator vhdl code

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Omar20

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hello guys i would like you guys to help me i am having an assignment and the lecturer ask me to design and implement a Simple Calculator Module in VHDL through the RTL (register Transfer Level) description and simulate the operations of this system in a suitable simulator. please guys help me i want the code for this calculator
 

FuzzySNR said:
Guy, post your code so far and and we will help guy.
Click to expand...

one of my friend send me this code but this code is only for GCD calculator but i need the code for simple calculator using RTL code
thank you for your fast respond and best regards
Code VHDL - [expand]
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-- Component: MULTIPLEXOR --------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
 
entity mux is 
    port(   rst, sLine: in std_logic;
        load, result: in std_logic_vector( 3 downto 0 );
        output: out std_logic_vector( 3 downto 0 )
    );
end mux;
 
architecture mux_arc of mux is
begin
    process( rst, sLine, load, result )
    begin
    if( rst = '1' ) then 
        output <= "0000";       -- do nothing
    elsif sLine = '0' then 
        output <= load;     -- load inputs
    else 
        output <= result;       -- load results
    end if;
    end process;
end mux_arc;
    
-- Component: COMPARATOR ---------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
 
entity comparator is
    port(   rst: in std_logic;
        x, y: in std_logic_vector( 3 downto 0 );
        output: out std_logic_vector( 1 downto 0 )
    );
end comparator;
 
architecture comparator_arc of comparator is
begin
    process( x, y, rst )
    begin
    if( rst = '1' ) then 
        output <= "00";     -- do nothing
    elsif( x > y ) then 
        output <= "10";     -- if x greater
    elsif( x < y ) then 
        output <= "01";     -- if y greater
    else 
        output <= "11";             -- if equivalance.  
    end if;
    end process;
end comparator_arc;
 
-- Component: SUBTRACTOR ----------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
 
entity subtractor is
    port(   rst: in std_logic;
        cmd: in std_logic_vector( 1 downto 0 );
        x, y: in std_logic_vector( 3 downto 0 );
        xout, yout: out std_logic_vector( 3 downto 0 )
    );
end subtractor;
 
architecture subtractor_arc of subtractor is
begin
    process( rst, cmd, x, y )
    begin
    if( rst = '1' or cmd = "00" ) then  -- not active.
        xout <= "0000"; 
        yout <= "0000";
    elsif( cmd = "10" ) then        -- x is greater
        xout <= ( x - y );
        yout <= y;
    elsif( cmd = "01" ) then        -- y is greater
        xout <= x;  
        yout <= ( y - x );
    else 
        xout <= x;              -- x and y are equal
        yout <= y;      
    end if;
    end process;
end subtractor_arc;
 
-- Component: REGISTER ---------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
 
entity regis is
    port(   rst, clk, load: in std_logic;
            input: in std_logic_vector( 3 downto 0 );
        output: out std_logic_vector( 3 downto 0 )
    );
end regis;
 
architecture regis_arc of regis is
begin
    process( rst, clk, load, input )
    begin
    if( rst = '1' ) then 
        output <= "0000";
    elsif( clk'event and clk = '1') then
        if( load = '1' ) then   
            output <= input;
        end if;
        end if;
    end process;
end regis_arc;
 
-- component: FSM controller --------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
 
entity fsm is
    port(   rst, clk, proceed: in std_logic;
        comparison: in std_logic_vector( 1 downto 0 );
        enable, xsel, ysel, xld, yld: out std_logic
    );
end fsm;
 
architecture fsm_arc of fsm is
 
    type states is ( init, s0, s1, s2, s3, s4, s5 );
    signal nState, cState: states;
 
begin
    process( rst, clk )
    begin
    if( rst = '1' ) then 
        cState <= init;
    elsif( clk'event and clk = '1' ) then 
        cState <= nState;
    end if;
    end process;
 
    process( proceed, comparison, cState )
    begin
    case cState is 
        
    when init =>    if( proceed = '0' ) then 
                nState <= init;
            else 
                nState <= s0;
            end if;
            
    when s0 =>  enable <= '0';
            xsel <= '0';
            ysel <= '0';
            xld <= '0';
            yld <= '0';
            nState <= s1;
    
    when s1 =>  enable <= '0';
            xsel <= '0';
            ysel <= '0';
            xld <= '1';
            yld <= '1';
            nState <= s2;
        
    when s2 =>  xld <= '0';
            yld <= '0';
            if( comparison = "10" ) then 
                nState <= s3;
            elsif( comparison = "01" ) then 
                nState <= s4;   
            elsif( comparison = "11" ) then 
                nState <= s5;       
            end if;
        
    when s3 =>  enable <= '0';
            xsel <= '1';
            ysel <= '0';
            xld <= '1';
            yld <= '0';
            nState <= s2;
    
    when s4 =>  enable <= '0';
            xsel <= '0';
            ysel <= '1';
            xld <= '0';
            yld <= '1';
            nState <= s2;
 
    when s5 =>  enable <= '1';
            xsel <= '1';
            ysel <= '1';
            xld <= '1';
            yld <= '1';
            nState <= s0;
            
    when others =>  nState <= s0;
            
        end case;
    
    end process;
    
end fsm_arc;
 
----------------------------------------------------------------------
-- GCD Calculator: top level design using structural modeling
-- FSM + Datapath (mux, registers, subtracter and comparator)
----------------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.all;
 
entity gcd is
    port(   rst, clk, go_i: in std_logic;
        x_i, y_i: in std_logic_vector( 3 downto 0 );
        d_o: out std_logic_vector( 3 downto 0 )
    );
end gcd;
 
architecture gcd_arc of gcd is
 
component fsm is
    port(   rst, clk, proceed: in std_logic;
        comparison: in std_logic_vector( 1 downto 0 );
        enable, xsel, ysel, xld, yld: out std_logic
    );
end component;
 
component mux is 
    port(   rst, sLine: in std_logic;
        load, result: in std_logic_vector( 3 downto 0 );
        output: out std_logic_vector( 3 downto 0 )
    );
end component;
 
component comparator is
    port(   rst: in std_logic;
        x, y: in std_logic_vector( 3 downto 0 );
        output: out std_logic_vector( 1 downto 0 )
    );
end component;
 
component subtractor is
    port(   rst: in std_logic; 
        cmd: in std_logic_vector( 1 downto 0 );
        x, y: in std_logic_vector( 3 downto 0 );
        xout, yout: out std_logic_vector( 3 downto 0 )
    );
end component;
 
component regis is
    port(   rst, clk, load: in std_logic;
        input: in std_logic_vector( 3 downto 0 );
        output: out std_logic_vector( 3 downto 0 )
    );
end component;
 
signal xld, yld, xsel, ysel, enable: std_logic;
signal comparison: std_logic_vector( 1 downto 0 );
signal result: std_logic_vector( 3 downto 0 );                  
 
signal xsub, ysub, xmux, ymux, xreg, yreg: std_logic_vector( 3 downto 0 );
 
begin
 
    -- doing structure modeling here
 
    -- FSM controller
    TOFSM: fsm port map(    rst, clk, go_i, comparison, 
                enable, xsel, ysel, xld, yld );                  
    -- Datapath
    X_MUX: mux port map( rst, xsel, x_i, xsub, xmux );
    Y_MUX: mux port map( rst, ysel, y_i, ysub, ymux );
    X_REG: regis port map( rst, clk, xld, xmux, xreg ); 
    Y_REG: regis port map( rst, clk, yld, ymux, yreg ); 
    U_COMP: comparator port map( rst, xreg, yreg, comparison );
    X_SUB: subtractor port map( rst, comparison, xreg, yreg, xsub, ysub );
    OUT_REG: regis port map( rst, clk, enable, xsub, result );
    
    d_o <= result; 
 
end gcd_arc;
 
---------------------------------------------------------------------------
 
Last edited by a moderator:

this is what i have done but there is 3 errors i could not find it please help me 

Code VHDL - [expand]
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Library IEEE;
Use IEEE.STD_CALC_PAK is
Package MY_CALC_PAK is
Type MY_RECORD is
Record
OP_CODE : std_logic_vector(3 downto 0); -- opcode 
A_IN : std_logic_vector(3 downto 0); --A operand
B_IN : std_logic_vector(3 downto 0); --B operand
C_IN : std_logic;   -- C_In operand
Exp out : std_logic_vector(3 downto 0); -- expected output 
End record;
end MY_CALC_PAk;
 
LIBRARY ieee;
USE ieee.std_logic_1164.all; 
USE ieee.std_logic_unsigned.all; 
USE ieee.numeric_std.ALL;
use CALC1_PAK.ALL;
ENTITY CNTRL_FSM_Tb-vhd IS
END CNTRL_FSM_TB_vhd;
ARCHITECTUTER behavior OF CNTRL_FSM_TB-vhd IS
 
-- Component Declaration for the Unit Under Test (UUT) 
COMPONENT CNTRL_FSM
PORT(
DATA_FRAME : IN MY_RECORD; 
CLK : IN std_logic;
RESET: IN std_logic;
MEM_EN : OUT std_logic;
ADDR : OUT std_logic_vector(3 downto 0); 
ALU_EN : OUT std_logic;
A_IN : OUT std_logic_vector(3 downto 0); 
B_IN : OUT std_logic_vector(3 downto 0); 
OP_CODE : OUT std_logic_vector(3 downto 0); 
C_IN    : OUT std_logic;
COMP_EN : OUT std_logic;
EXP : OUT std_logic_vector(3 downto 0);
 );
END COMPONENT;
-- Inputs
SIGNAL DATA_FRAME : MY-RECORD :=
(A_IN=> *0111*, B_IN=>*0011*, 
OP_CODE =>*0000*, C_IN=> ‘0’, EXP_OUT=>”0111”); 
SIGNAL CLK : std_logic :=’0’;
SIGNAL RESET: std_logic :='0';
-- Outputs
SIGNAL MEM_EN : std_logic;
SIGNAL ADDR : std_logic_vector(3 downto 0); 
SIGNAL ALU_EN : std_logic;
SIGNAL A_IN : std_logic_vector(3 downto 0); 
SIGNAL B_IN : std_logic_vector(3 downto 0);
SIGNAL OP_CODE : std_logic_vector(3 downto 0); 
SIGNAL C_IN : std_logic;
SIGNAL COMP_EN : std_logic;
SIGNAL EXP : std_logic_vector(3 downto 0);
 
BEGIN
    -- Instantiate the Unit Under Test (UM)
uut: CNTRL_FSM PORT MAP(
DATA_FRAME => DATA_FRAME,
CLK => CLK 
RESET => RESET.
MEM_EN => MEM_EN.
ADDR => ADDR. 
ALU_EN => ALU_EN,
A IN => A_IN, 
B_IN => B_IN,
OP_CODE => OP_CODE,
C_IN => C_IN,
COMP EN => COMP_EN,
EXP=>EXP
    );
CLK <= not CLK after 10 ns; -- 50 MHz clock
RESET <= '0','1' after 10 ns, '0' after 25ns, '1' after 800ns, '0' after 825ns;
    --test_proc : PROCESS
    --BEGIN
 
tb : PROCESS
BEGIN
DATA_FRAME <= ("1000", "0100", "0000", "0000");
wait for 100 ns;
DATA_FRAME <=("1000","0100”,”0101","0","0000”); 
wait for 100 ns;
DATA_FRAME <=("1000","0100","0101","0","0000"); 
Wait; - will wait forever
--END PROCESS test-proc;
END;
 
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use MY_CALC_PAK.ALL
entity CNTRL_FSM is
port (DATA_FRAME : in MY_RECORD;
CLK : in STD_LOGIC;
RESET: in STD_LOGIC;
MEM-EN: out STD_LOGIC;
ADDR : out STD_LOGIC_VECTOR(4 downto 0); 
ALU_EN : out STD_LOGIC;
A_IN: out STD_LOGIC_VECTOR(3 downto 0);
B_IN: out STD_LOGIC_VECTOR(3 downto 0); 
OP_CODE : out STD_LOGIC_VECTOR(3 downto 0); 
C_IN : out STD_LOGIC;
COMP EN : out std_logic;
EXP : out std_logic_vector(3 downto 0);
end CNTRL_FSM;
architecture Behavioral of CNTRL_FSM is
type State is (INIT, FETCH, ALU, COMP, DONE); 
signal Curr_State, Next_State: State;
signal ADDR_INT : std_logic_vector(4 downto 0); 
signal ADDR_Q : std_logic_vector(4 downto 0);
begin
ADDR <= ADDR_Q
Sync: process (CLK.RESET)
begin
if RESET = T then
Curr_State <= Next_State;
ADDR_Q <= (others => '0')
else if rising_edge(CLK) then
curr_State <= Next_State;
ADDR_Q <= ADDR_INT:
end if;
end process Syne;
find_Next_State: process (Curr_State,DATA_FRAME,ADDR_Q) 
begin
A_IN <= DATA_FRAME.A_IN; 
B_IN <= DATA_FRAME.B_IN; 
C_IN <= DATA_FRAME.C_IN; 
OP_CODE <= DATA_FRAME.OP_CODE;
ADDR_INT <= ADDR Q
EXP<= DATA_FRAME.EXP_OUT;
 
case (Curr_State) is
when INIT => -- set up initial defaults 
MEM_EN <= '0';
Alu_en <= '0'; 
COMP_EN <= '0';
ADDR INT <= (others => '0' );
Next State <= FETCH;
when FETCH =>
MEM_EN <= '1';
ALU_EN <= '0'; 
COMP_EN <= '0'; 
Next State <= ALU;
 
when ALU =>
MEM_EN <= '0';
ALU_EN <= '1';
COMP_EN<= '0'; 
Next State <= COMP;
 
when COMP =>
MEM_EN <= '0';
ALU_EN <= '0'; 
COMP_EN <= '1';
 
when DONE =>
MEM_EN <= '0';
ALU_EN <= '0';
COMP_EN <= '0';
IF ADDR_Q <= "11111" then
ADDR INT <= ADDR Q + '1';
 
Next _state <= FETCH;
 else
Next _State <= DONE;
end if;
 
when others =>
MEM_EN<= '0';
ALU_EN <= '0';
COMP_EN<= '0’;
Next _State <= INIT; 
end case;
end process Find_Next_State;
end BEhavioral:
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD LOGIC_UNSIGNED.ALL;
entity COMP is
port (COMP_EN : in STD_LOGIC;
CLK : in STD LOGIC,
EXPECTED: in STD_LOGIC_VECTOR(3 downto 0); 
ALU_OUT : in STD_LOGIC_VECTOR(3 downto 0);
RESULT: out STD_LOGIC;
End COMP;
 
 
Architecture RTL of COMP is 
Begin
Process (CLK)
Begin
If rising_edge(CLK) then
If comp_en = '1' then
If ALU_OUT = EXPECTED then 
RESULT <= ' l';
Else
RESULT <= '0';
End if;
End if;
End if;
End process;
End RTL;
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL; 
USE ieee.std_logic_unsigned.all; 
USE ieee.numeric_std.ALL;
ENTITY COMP TB_vhd IS 
END COMP TB vhd;
ARCHITECTURE test OF COMP_TB_vhd IS
 
-- Component Declaration for the Unit Under Test (UUT) 
COMPONENT COMP
 
PORT(
COMP_EN : in STD_LOGIC;
CLK : in STD_LOGIC;
EXPECTED: in STD_LOGIC_VECTOR(3 downto 0); 
ALU_OUT : in STD_LOGIC_VECTOR(3 downto 0); 
RESULT: out STD_LOGIC
);
END COMPONENT,
-- inputs
SIGNAL COMP_EN: std_logic : = '1'
SIGNAL CLK : std_logic : = '0'
SIGNAL EXPECTED: std_logic_vector(3 downto 0);= "0001"; 
SIGNAL ALU_OUT : std_logic_vector(3 downto 0);= "0001";
--Output
SIGNAL RESULT: std_logic;
BEGIN
--Instantiate the Unit Under Test (UUT) 
uut: COMP PORT MAP(
COMP_EN => COMP_EN, 
CLK => CLK,
EXPECTED => EXPECTED, 
ALU_OUT => ALU_OUT, 
RESULT => RESULT
);
CLK <= not CLK after l0ns;
test_proc : PROCESS
BEGIN
Wait for 5ns
Expected <= "0010" after 100ns
Wait;
END PROCESS test_proc;
END;
 
library IEEE;
use IEEE.STD_LOGIC_I164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IFEE.STD_LOGIC_UNSIGNED.ALL;
use MY_CALC_PAK.ALL;
 
Entity MY_CALC is
generic (SYNTH: Boolean := false);
Port (CLK : in STD_LOGIC; 
RESET: in STD_LOGIC; 
RESULT: out STD_LOGIC;
and MY_CALC);
architecture Structural of MY_CALC is
component MEM
port (CLK : in STD_LOGIC;
ADDR : in STD_LOGIC_VECTOR (4 downto 0); 
READ_EN : in STD_LOGIC;
DATA_FRAME : out MY_RECORD);
End component;
Component CNTRL_FSM
Port (DATA_FRAME : in MY RECORD
CLK : in STD_LOGIC;
RESET: in STD_LOGIC;
MEM_EN : out STD_LOGIC
ADDR : out STD_LOGIC_VECTOR(4 downto 0); 
ALU_EN : out STD_LOGIC
A_IN : out in STD_LOGIC_VECTOR(3 downto 0); 
B_IN : out STD_LOGIC_VECTOR(3 downto 0); 
OP_CODE : out STD LOGIC_VECTOR(3 downto 0); 
C_IN : out STD_LOGIC;
COMP_EN : out std_logic;
EXP : out std_logic_vector(3 downto 0);
End component;
Component ALU
Port (A : in STD_LOGIC_VECTOR(3 downto 0);
 
 
B: in STD_LOGIC_VECTOR(3 downto 0);
C_IN : in STD_LOGIC
OP_CODE : in STD_LOGIC_VECTOR(3 downto 0); 
CLK : in STD_LOGIC
ALU_EN : in STD_LOGIC
ALU OUT : out STD_LOGIC_VECTOR(3 downto 0)); 
End component;
 
Component COMP
Port (COMP_EN : in STD_LOGIC;
CLK : in STD_LOGIC
EXPECTED: in STD_LOGIC_VECTOR(3 downto 0); 
ALU_OUT : in STD LOGIC_VECTOR(3 downto 0); 
RESULT: out STD_LOGIC);
End component;
Signal DATA_FRAME_SIG : MY RECORD;
Signal ADDR_SIG : STD LOGIC VECTOR(4 downto 0);
Signal MEM_EN_SIG, ALU_EN_SIG, COMP_EN_SIG, C_IN_SIG : std logic; 
Signal A-IN_SIG, B_IN_SIG, OP_CODE_SIG, EXP_OUT_SIG, ALU_OUT_SIG;
STD_LOGIC_VECTOR(3 downto 0);
Begin
U1 : MEM port map
(CLK=>CLK.ADDR=>ADDR_SIG.READ_EN=>MEM_EN_SIG.DATA_FRA 
ME=>DATA_FRAME_SIG):
U2 : CNTRL_FSM port map
(DATA_FRAME=>DATA_FRAME_SIG,CLK=>CLK,RESET=>RESET, MEM_EN=>MEM_EN_SIG,
ADDR=>ADDR_SIG,ALU_EN=>ALU_SIG,A_IN=>A_IN_SIG, B_IN=>B_IN_SIG,OP_CODE=>OP_CODE_SIG.
C_IN=>C_IN_SIG,COMP_EN=>COMP_EN_SIG,EXP=>EXP_OUT_SIG);
 
 
U3 : ALU port map (A=>A_IN_SIG,B=>B_IN_SIG,CLK=>CLK,EXPECTED=>EXP_OUT_SIG,ALU_OUT=>ALU_OUT_SIG,
RESULT=>RESULT);
End Structural;
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL; 
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY MY_CALC_TB_vhd IS
END MY_CALC_TB_vhd;
ARCHITECTURE test OF MY_CALC_TB_vhd IS
COMPONENT MY_CALC
PORT(
CLK_IN : IN std_logic;
RESET :IN std_logic;
RESULT_OUT : OUT std_logic
);
END COMPONENT; --Input
SIGNAL CLK : std_logic : = '0'; 
SIGNAL RESET_TB : std_logic = '0';
 
-- Output 
SIGNAL RESULT: std_logic;
 
BEGIN
-- Instantiate tk Unit Under Test (UM) 
Uut: MY_CALC PORT MAP(
CLK_IN=>CLK_TB,
RESET=>RESET_TB
RESULT_OUT=>RESULT 
);
 
CLK_TB <= not CLK_TB after lOns;
RESET_TB <= T after 15ns, '0' after 25ns, T after 700ns, ‘0’ after 725 ns,
End architecture TEST;
 
USE ieee.std_lOgic_1164.ALL;
USE ieee.std_lOgic_unsigned.all;
USE ieee.numeric_std.ALL;   
 
ENTITY ALU_TB_VHD IS    
END ALU_TB_VHD;
 
Architecture behavior OF ALU_TB_vhd IS
-- Component Declaration for the Unit Unver Test (UM) COMPONENT ALU
PORT(
A: IN std_logic_vector(3 downto 0); 
B: IN std_logic_vector(3 downto 0);
C_IN : IN std_logic;
OP_CODE : IN std_logic_vector(3 downto 0); 
CLK: IN std_logic;
ALU_EN : IN std_logic;
ALU_OUT : OUT std_logic_vector(3 downto 0);
);
END COMPONENT;
 
SIGNAL C_IN : std_logic : = ‘0';  -- nput signals
SIGNAL CLK : std_logic : = '0';
SIGNAL ALU_EN: std_logic : = '1';
SIGNAL A : std_logic_vector(3 downto 0) : = "0111"; 
SIGNAL B : std_logic_vector(3 downto 0) : = "0011"; 
SIGNAL OP_CODE : std_logic_vector(3 downto 0) : = (others=>'0'); 
SIGNAL alu_out : std_logic_vector(3 downto 0);
BEGIN
    -- Instantiate the Unit Under Test (UUT) 
    Uut: ALU PORT MAP(
A => A
B => B,
C_IN => C_IN,
OP_CODE => OP_CODE,
CLK => CLK,
ALU_EN => ALU_EN,
ALU_OUT => ALU_OUT
 
CLK <= not CLK after 5ns;
 
 
Test_proc : PROCESS
BEGIN
OP_CODE (3 downto 0) <= "0000"; --Ix a 
C_IN <= '0';
wait for 20ns;
OP_CODE (3 downto 0) <= "0001";  --txa .
C_IN <= '1';
wait for 20ns;
OP_CODE (3 downto 0) <= "0001";  --inc 
C_IN <= '0';
wait for 20ns;
OP_CODE (3 downto 0) <= "0001"; --inc .
C_IN <= '1';
wait for 20ns;
OP_CODE (3 downto 0) <= "0010"; --add 
C_IN <= '0';
wait for 20ns;
OP_CODE (3 downto 0) <= "0010"; --add 
C_IN <= '1';
wait for 20ns;
OP_CODE (3 downto 0) <= "0011"; --adde 
C_IN <= '0';
wait for 20ns;
OP_CODE (3 downto 0) <= "0011"; --adde 
C_IN <= '1';
wait for 20ns;
OP_CODE (3 downto 0) <= "0100"; --sub 
C_IN <= '0'; 
wait for 20ns; 
OP_CODE (3 downto 0) <= "0100"; --sub 
C_IN <= ' 1 '; 
wait for 20ns: 
OP_CODE (3 downto 0) <= "0101"; --comp 
C_IN <= '0'; 
wait for 20ns; 
OP_CODE (3 downto 0) <= "0101"; --comp 
C_IN <= '1'; 
wait for 20ns; 
OP_CODE (3 downto 0) <= "0110"; --neg 
C_IN <= '0'; 
wait for 20ns; 
OP_CODE (3 downto 0) <= "0110"; --neg 
C_IN <= '1'; 
wait for 20ns; 
OP_CODE (3 downto 0) <= "0111"; --dec 
C_IN <= '0'; 
wait for 20ns; 
OP_CODE (3 downto 0) <= "0111"; --dec 
C_IN <= '1'; 
wait for 20ns; 
OP_CODE (3 downto 0) <= "1000"; --txb
C_IN <= ‘0’;
wait for 20ns;
OP_CODE (3 downto 0) <= “1000”; --txb
C_IN <= ‘1’;
wait for 20ns;
OP_CODE (3 downto 0) <= “1001”; --and
C_IN <= '0';
wail for 20ns;
OP_CODE (3 downto 0) <= “1001”; --and
C_IN <= ‘1’;
wait for 20ns;
OP_CODE (3 downto 0) <= “1010”; --or'
C_lN <= ‘0’;
wait for 20ns;
OP_CODE (3 downto 0) <= “1010”; --or
C_lN <= ‘1’;
wait for 20ns;
OP_CODE (3 downto 0) <= "1011"; --X01’
C_IN <= ‘0’;
wait for 20ns;
OP_CODE (3 downto 0) <= "1011"; --X01’
C_lN <= ‘l';
wait for 20ns;
OP_CODE (3 downto 0) <= “1100”; --sl
C_IN <= ‘0’;
wait for 20ns;
OP_CODE (3 dowNTo 0) <= “1100”; --sl
C_IN <= ‘1’;
wait for 20ns;
OP_CODE (3 downto 0) <= “1101”; --sr
C_IN <= ‘0’;
wait for 20ns;
OP_CODE (3 downto 0) <= “1101”; --sr
C_IN <= ‘1’;
wait for 20ns;
OP_CODE (3 downto 0) <= “1110”; --par
C_IN <= ‘0’;
wait for 20ns;
OP_CODE (3 downto 0) <= “1111”; --um
C_lN <= ‘0’;
wait for 20ns;
OP_CODE (3 downto 0) <= “1111”; --zero
C_lN <= ‘1';
wait for 20ns;
wait;
EnD PROCESS tes_proc;
 
END;
 
library IEEE;           --Library Declaration
use IEEE.STD_LOGIC_1164.ALL;    --Packed Declaration
use IEEE.STD_LOGIC_ARITH.ALL;       --Packed operation and function
use IEEE.STD_LOGIC_UNSIGNED.ALL; 
--Packagesstd_logic_vector
 
use work. MY_CALC_PAK.ALL;
 
 
Entity MEM_TB is    -- Primary design unit MEM
End MEM_TB; -- Close entity declaration
 
Architecture test of MEM_TB is -- Secondary design unit
 
Component MEM
Port (CLK : in STD_LOGIC;
ADDR : in STD_LOGIC_VECTOR (4 downto 0); 
--Port declaration
READ_EN : in STD_LOGIC;
DATA_FRAME: out MY_RECORD);
End component;
 
Signal CLK; std_logic ;='0'
Signal ADDE_SIG : std_logic_vector (4 downto 0) = "0000"; --local signals
Signal READ_EN_SIG :std_logic ;= '1';
Signal DATA_FRAME_SIG : MY_RECORD;
 
Begin           -- Begin Architecture
 
Uut: MEM port map (CLK => CLK,
ADDR => ADDR_SIG,   -- unit under testing for testing
READ_EN => READ_EN_SIG,
    
DATA_FRAME =>DATA_FRAME_SIG); 
CLK <= not CLK after lOns;
Process
Begin   --Begin the process
ADDR_SIG <= "00000"; wait for 100ns; 
ADDR_SIG <= "00001"; wait for 100ns; 
ADDR_SIG <= "00010"; wait for 100ns; 
ADDR_SIG <= "00100"; wait for 100ns; 
ADDR_SIG <= "00101"; wait for 100ns; 
ADDR_SIG <= "00110"; wait for 100ns; 
ADDR_SIG <= "00111"; wait for 100ns;
ADDR_SIG <= "01000"; wait for 100ns; 
ADDR_SIG <= "01001'; wait for 100ns;
ADDR_SIG <= "01010"; wait for 100ns; --Statements operate sequentially ADDR_SIG <= "01011"; wait for 100ns;
ADDR_SIG <= "01100"; wait for 100ns; 
ADDR_SIG <= "01101"; wait for 100ns; 
ADDR_SIG <= "01110"; wait for 100ns; 
ADDR_SIG c= "01111"; wait for 100ns; 
ADDR_SIG <= "10000"; wait for 100ns; 
ADDR_SIG <= "10001"; wait for 100ns; 
ADDR_SIG <= "10010"; wait for 100ns; 
ADDR_SIG <= "10011"; wait for 100ns; 
ADDR_SIG <= "10100"; wait for 100ns; 
ADDR_SIG <= "10101"; wait for 100ns; 
ADDR_SIG <= "10110"; wait for 100ns; 
ADDR_SIG <= "10111"; wait for 100ns; 
ADDR_SIG <= "11000"; wait for 100ns;
ADDR_SIG <= "11001"; wait for 100ns; 
ADDR_SIG <= "11010"; wait for 100ns;
ADDR_SIG <= “11011"; wait for l00ns;
ADDR_SIG <= “l1100"; wait for l00ns;
ADDR_SIG <= “l1101"; wait for l00ns;
ADDR_SIG <= “11110"; wait for 100n5;
ADDR_SIG <= “11111"; wait for 100n5;
 
Wait;
 
End process; -- End pmoess
End architecture  test; -- End the body amhiecnue
 
 
(0 =>
(OP_CODE=>”0000",A_IN =>”0111",B_IN=>”0011”,c_in=>’0’,EXP_OUT=>"0111"), --txa
l =>
(OP_CODE=>”0000”,A_IN =>”0111”,B_IN=>”0011”,c_in=>’0’,EXP_0UT=>”0111”), --tn
2 =>
(OP_CODE=>”0001”,A_IN=>”0111”,B_IN=>”0011”,c_in=>’0’,EXP_OUT=>”1000"), --inc
3 =>
(OP_CODE=>”000l”,A_IN=>”0111”,B_IN=>”0011”,c_in=>’0’,EXP_OUT=>”1000”), --inc
4 =>
(OP_CODE=>”00l0”,A_IN=>”0111",B_IN=>”0011”,c_in=>’0’,EXP_0UT=>”1010”), --add
5 =>
(OP_CODE.=>”00l0",A_IN=>”0111”,B_IN=>”0011”,c_in=>’0',EXP_0UT=>”l0l0"), --add
6 =>
(OP_CODE=>”001l”,A_IN=>”0111",B_IN=>”0011",c_in=>’0',EXP_0UT=>"l010”), --addc
7 =>
(OP_CODE=>"0011”,A_IN=>”0111”,B_IN=>”0011”,c_in=>’0’,EXP_0UT=>"1011”), --addc
8 =>
(OP_CODE=>"0100”,A_IN=>”0111",B_IN=>”0011”, c_in=>’0’,EXP_0UT=>"0100”), --sub
9 =>
(OP_CODE.=>”0100”,A_IN=>”0111",B_IN=>"0011”, c_in=>’0’,EXP_0UT=>"0100”), --sub
10 =>
(OP_CODE=>"0101”,A_IN=>”0111",B_IN=>”0011”, c_in=>’0’,EXP_0UT=>"1000”), --Comp
11 =>
(OP_CODE=>"0111",A_IN=>”0111”,B_IN=>”0011”, c_in=>’0’,EXP_0UT=>"1000”), --Comp
12 =>
(OP_CODE=>”0110”,A_IN=>”0111",B_IN=>”0011", c_in=>’0’,EXP_0UT=>"1001”), --neg
13 =>
(OP_CODE=>”0110”,A_IN=>”0111",B_IN=>”0011”, c_in=>’0’,EXP_0UT=>"1001”), --neg
14 =>
(OP_CODE=>”0111”,A_IN=>”0111",B_IN=>"0011", c_in=>’0’,EXP_0UT=>"0110”), --dec
15 =>
(OP_CODE=>”0111”,A_IN=>”0111",B_IN=>”0011”, c_in=>’0’,EXP_0UT=>"0110”), --dec
16 =>
(OP_CODE=>”1000”,A_IN=>”0111",B_IN=>"0011", c_in=>’0’,EXP_0UT=>"0011”), --txb
17 =>
(OP_CODE=>"1000”,A_IN=>”0111”,B_IN=>”0011",c_in=>’0’,EXP_0UT=>"0011”), --txb
18 =>
(OP_CODE=>"1001”,A_IN=>”0111”,B_IN=>”0011",c_in=>’0’,EXP_0UT=>"0011”),  --and
I9 =>
(OP_CODE=>"1001”,A_IN=>”0111”,B_IN=>”0011",c_in=>’0’,EXP_0UT=>"0011”), --and
20 =>
(OP_CODE=>"1010”,A_IN=>”0111”,B_IN=>”0011",c_in=>’0’,EXP_0UT=>"0111”), --or
21 =>
(OP_CODE=>"1010”,A_IN=>”0111”,B_IN=>”0011",c_in=>’0’,EXP_0UT=>"0111”), --or
22 =:>
(OP_CODE=>"1011”,A_IN=>”0111”,B_IN=>”0011",c_in=>’0’,EXP_0UT=>"0100”), --xor
23 =>
(OP_CODE=>"1011”,A_IN=>”0111”,B_IN=>”0011",c_in=>’0’,EXP_0UT=>"0100”),  --xor
24 =>
(OP_CODE=>"1100”,A_IN=>”0111”,B_IN=>”0011",c_in=>’0’,EXP_0UT=>"1110”), --sl
25 =>
(OP_CODE=>"1100”,A_IN=>”0111”,B_IN=>”0011",c_in=>’0’,EXP_0UT=>"1110”), --sl
26 =>
(OP_CODE=>"0011”,A_IN=>”0111”,B_IN=>”0011",c_in=>’0’,EXP_0UT=>"0011”),  --sr
27 =>
(OP_CODE=>"1101”,A_IN=>”0111”,B_IN=>”0011",c_in=>’0’,EXP_0UT=>"0011”), --sr
28 =>
(OP_CODE=>"1110”,A_IN=>”0111”,B_IN=>”0011",c_in=>’0’,EXP_0UT=>"0001”),  --Par
29 =>
(OP_CODE=>"1110”,A_IN=>”0111”,B_IN=>”0011",c_in=>’0’,EXP_0UT=>"0000”), --Par
30 =>
(OP_CODE=>"1111”,A_IN=>”0111”,B_IN=>”0011",c_in=>’0’,EXP_0UI'=>"0000”),  --zero
31 =>
(OP_CODE=>"1111”,A_IN=>”0111”,B_IN=>”0011",c_in=>’0’,EXP_0UI'=>"0000”),  --zero
 
Last edited by a moderator:

Re: vhdl code for simple calculator

Don't just copy paste... just post where your getting simulation errors. This code is only for simulation purpose and it will not synthesize any hardware.
 

Re: vhdl code for simple calculator

this is the message i keep getting when i try to compile the file
vcom -work work -2002 -explicit {C:/Modeltech_pe_edu_10.2c/examples/assignment vhdl.vhd}
Model Technology ModelSim PE Student Edition vcom 10.2c Compiler 2013.07 Jul 18 2013
-- Loading package STANDARD
** Error: (vcom-11) Could not find ieee.std_calc_pak.

** Error: C:/Modeltech_pe_edu_10.2c/examples/assignment vhdl.vhd(2): (vcom-1195) Cannot find expanded name "ieee.STD_CALC_PAK".

** Error: C:/Modeltech_pe_edu_10.2c/examples/assignment vhdl.vhd(2): near "is": expecting '[' or '(' or '.' or '\''
 

Re: vhdl code for simple calculator

if your compiled library is work then code like use work.std_calc_pak.all
 

my friend i added this code MY_CALC_PACKAGE.vhd: in the beginning of the code and i decrease the number of error to 1 error

MY_CALC_PACKAGE.vhd :
Code VHDL - [expand]
1
2
3

Library IEEE;
Use IEEE.STD_CALC_PAK is
Package MY_CALC_PAK is


this is the error i get now

Code: 
vcom -work work -2002 -explicit {C:/Modeltech_pe_edu_10.2c/examples/assignment vhdl.vhd}
Model Technology ModelSim PE Student Edition vcom 10.2c Compiler 2013.07 Jul 18 2013
-- Loading package STANDARD
** Error: C:/Modeltech_pe_edu_10.2c/examples/assignment vhdl.vhd(1): near "MY_CALC_PACKAGE": syntax error
 
Last edited by a moderator:

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