Signal prdata cannot be synthesized, bad synchronous description.

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Hi,

I am trying to run synthesis on the following simple code fragement, where I wanna
assign the output signal "prdata" on the rising edge of the clock:

Code: 
entity ipic_if is
    port (
        ....
        prdata        : out std_logic_vector(0 to 31);
        ....
   );
  
  .....

  READ_REGISTER_PROCESS : process(clk)
  begin
    if (clk'event and clk = '1') then
       if reset = '1' then
              prdata <= (others => '0');
       end if; 
    else      
	case paddr(8 downto 2) is
			  when "1000001" => prdata <= Dout;
			  when "1000011" => prdata <= (Z(0 to 26) & test(0 to 4));
                          ...
			  when others      => prdata <= (others => '0');
	end case;	
    end if;
   end process READ_REGISTER_PROCESS;

ERROR:Xst:827 - Signal prdata cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.

Anyone an idea why XST does not like this description? It works fine for simulation...
 

Hi,

Remove the "end if" below the line "pr_data <= (others => '0'); as shown below:

READ_REGISTER_PROCESS : process(clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
prdata <= (others => '0');
else
case paddr(8 downto 2) is
when "1000001" => prdata <= Dout;
when "1000011" => prdata <= (Z(0 to 26) & test(0 to 4));
...
when others => prdata <= (others => '0');
end case;
end if;
end process READ_REGISTER_PROCESS;


As you close the "if reset" statement with "end if", your else with case statement is not part of the rising edge of clk and results in a bad synchronous description error.

Devas
 
Thanks Devas, quite embarrassing that I could not seen this myself. Seems an error to easy to be spotted for me .
 

Hello
I have the same problem. I'm new to VHDL. I tried to find what is wrong but I have no idea. When I'm compiling only this part of code everything looks to be OK, but while compiling whole project I get "Signal prdata cannot be synthesized, bad synchronous description." Pls help me...

code:
Code: 
zapis :process(WRI,CLK2)
	variable i,j : integer:= 0;
	begin
	if rising_edge(WRI) then
		j := 1;
		ADRS <= (others => '0');
	--end if;
	elsif CLK2 = '1' and j = 1 then
		i := i +1;
		if i < 40000 then
			DT2 <= "101";
			ADRS <= ADRS + 1;
		else
			i := 0;
			j := 0;
		end if;
	elsif CLK = '1' then
		ADRS <= ADRS + 1;
	end if;
	
	if ADRS = 39999 and CLK = '1' then
		ADRS <= (others => '0');
	end if;
		
end process;
 

Your process design is completely wrong, it can't be easily corrected. I suggest to think about the intended purpose of the code, consulting a VHDL text book or tutorial how things can be done.

A basic point is this:
An signal assignment like ADRS <= ADRS + 1; can be only done inside a clock edge sensitive block (e.g. if risisng_edge() ..), but not under an if CLK = '1' condition. The former counts up, one per clock edge, the latter would cause ADRS to go through all possible values in no time (which is physically impossible, of course).
 
try to avoid using multiple clocks, as well as level-sensitive clocks. The error is most likely on ADRS, which contains a combinatorial loop (if clk=1, adrs will attempt to increment until clk = 0). depending on the HW, it might not be synthesizable even if the combinatorial loop is removed. The register's clock input would need to be connected to WRI in order to get a rising edge. the register would then need to be controlled through async set and async reset pins. If the FPGA's registers only have a single async set/reset pin, then there would not be a way to implement the design*.

Try using just 1 clock, a rising edge, and using a single signal for reset, either sync or async. as always, async signals can cause a design running at any clock rate to fail.

*well, i guess there could be, but nothing reasonable.
 
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    cineq

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hmmm I thought that ADRS will increment only once after the delta time... if I use variable instead of signal and at the end of the proces I'll write ADRS <= variable ?? will it help?
Code: 
zapis :process(CLK2)
	variable adres : STD_LOGIC_VECTOR (15 downto 0):=(others => '0');
	variable i,j : integer:= 0;
	begin
	if CLK2 = '1' and WRI = '1' and WRI'event then
		j := 1;
		adres := (others => '0');
	end if;
	if CLK2 = '1' and j = 1 then
		i := i +1;
		if i < 10 then
			DT2 <= "101";
			adres := adres +1 ;
		else
			i := 0;
			j := 0;
		end if;
	end if;
	if CLK2 = '1' then
		adres := adres + 1;
	end if;
	
	if adres = 10 and CLK = '1' then
		adres := (others => '0');
	end if;
	ADRS <= adres;	
end process;

The program now is compilling this part...
 

the code might simulate, but not synthesize. The synthesizer ignores the sensitivity list. This means that the adres := adres +1 will still be a combinatorial loop.

the other comments also stand. WRI most likely should not be edge-sensitive. CLK2 should be edge sensitive. CLK should also not be used for adres. There are likely issues with WRI and CLK as well -- I suspect these are asynchronous to CLK2.
 
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    cineq

    Points: 2
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Unless you follow the synthesis templates, you cannot expect decent (or even legal) logic. The synchronous template is:

Code: 
process(clk, reset)
begin
  if reset = '1' then 
    --do your reset here
  elsif rising_edge(clk) then
    --All synchronous logic goes here
  end if;

  --Dont put logic here or inside the above if conditions - it probably wont be synthesisable or do what you expect
end process;
 
Im just curious if sync reset is more recommended than async ??
 

sync resets -- easy to analyze for timing. If the clock can be slow/gated/stopped, the reset could be missed. Because it is analyzed for timing, it can become a critical net.
async resets -- will always reset the logic, even when the clock is gated/stopped. The deassertion of reset is likely to be affected by skew and metastability. any registers that can change 1 (or more for high-skew cases) cycles after reset could either transition or not, based on the value of reset at that location of the IC.

For example, a down-counter that resets to 10000000. the logic will be X + 11111111. After reset, the value might be 00000000 (the MSB toggles to the next value, while reset is still affecting the other LSBs), 11111111 (the MSB is affected by the reset, but no other bits are), or any other value (some combination of bits affected, and other bits not affected). It can also move to a metastable state, where the value of a bit slowly transitions to a 1 or 0, or ends up at some value in-between. If this signal is used in multiple locations on the chip, it may end up being interpreted as different values in each location.

For Xilinx designs, some elements do not have async resets but do have sync resets. For example, DSP slices.

One common "safe" reset is made up of a shift register (2+) with an async set, and a '0' as the input. This forces a reset to assert, even if a clock isn't present, but also forces the de-assertion of reset to be synchronous.
 
hi,i'm newbie in vhdl and have same problem. i've lookin for error but i can't find it in this code:
Code: 
process (maxmin_out_sig, reset)	
	begin
		if (reset='1') then
				PWM_out_sig<='0';
			elsif (rising_edge (maxmin_out_sig)) then
			PWM_out_sig<=PWM_out_sig;
				else
				PWM_out_sig<=not(PWM_out_sig);
		end if;
	end process;
it says "Signal PWM_out_sig cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release"
 

remove the else section.
Think about it, what you are asking it to do is to constantly invert itself unless unless there is a rising edge on maxmin_out_sig (ie, its stops inverting itself for an extremly small length of time.

Read up on digital design, and following the coding templates. Also, its not recommended to use other signals as clocks in FPGAs. you have maxmin_out_sig as a clock here.
 
hi..
this error will come only when
positive edge some condition is running and you will try to do something in negative edge also...
try to assign only in positive or negative edge..
 
Last edited:
thanks mate, i forget about the negative edge as sanju_ said,,fix it and run smooth
 

Hi !
I'm new to VHDL ... & the same problem !
cand anyone help me ?
code :


architecture Behavioral of qam is

begin

process(clk,Input)
begin

if rising_edge(clk) then

-- wait until (clk'event and clk='1');
case Input is

when "00" =>
I_out <= 1;
Q_out <= 1;
when "01" =>
I_out <= -1;
Q_out <= 1;
when "10" =>
I_out <= 1;
Q_out <= -1;
when "11" =>
I_out <= -1;
Q_out <= -1;
when others=>
I_out<= 0;
Q_out<= 0;

end case;

else
I_out<= 0;
Q_out<= 0;

end if;

end process;

end Behavioral;


Signal Q_out cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.
thanks in advance
 

Perhaps you have an idea what the else clause should be good for?
Code: 
else
I_out<= 0;
Q_out<= 0;
I don't see a reasonable purpose. In any case it's not synthesizable and causing the reported error.
 

In VHDL REAL data type is not synthesizable,if you are using real on constants then there is no problem but if you are using it on signals or any other places ,then It will not be synthesizable in simple way.....If this is the problem ...
then there are ways to sort out this......check it
 

There are no real signals in the design. Integer is synthesizable.
 

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