[General] Signal input voltage near midpoint

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Well known that CMOS gates should always be driven high or low and not allowed to have floating inputs causing excessive shoot-through current in the output stage.

What if the input is not a logic gate per se, but simply a digital input to a microcontroller, and the input signal (from the external world) has very slow transitions or sits at mid-scale?

Will this damage the device in the long term or is the current limited sufficiently in the FET immediately after the input stage?

Assume this is a regular digital input (no hysteresis) and the signal ends up being midscale regardless of pull-ups
 

The "should always be driven" rule also applies to microcontroller GPIOs, unless the digital input circuit can be disabled, as e.g. for pins with optional analog function. The unwanted input stage current won't be high enough to damage the part, but sufficient to ruin the operating time of a battery supplied device.
 

Hi,

afaik it is the input stage of a logic gate that causes "crow bar currents".
On some logic devices it may cause the output to oscillate, (caused by internal or external capacitive coupling).

As FvM mentionend it will not damage the part, but you will see bigger EMI problems, increased current and an unreliable digital value.
To avoid this use inputs with schmitt-trigger functionality, or external schmitt-trigger device (74HC1G14...) or use a comparator (external or internal).

Klaus
 

Although ST inputs avoid the problem of possible oscillations, they still show increased supply current around the threshold voltage.
 

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