Signal Connected to Multiple Drivers Help?

p_label : process ( clk ) is
begin
  if rising_edge(clk) then
    -- defaults
    valid_out <= '0';
    data_out <= data_in;
    -- logic
    -- This logic sends a valid pulse for every other valid_in.
    -- The value of cnt will be retained (unless reset).
    -- The value of "valid_out" will transition back to 0 if these conditions aren't met (due to default)
    if valid_in = '1' then
      if cnt = 1 then
        valid_out <= '1';
      end if;
      cnt <= (cnt + 1) mod 2;
    end if;
    -- resets, sync
    -- this infers a reset on the register "valid_out" and "cnt"
    -- no register is applied to the registers "data_out".  
    -- This style of resets is common in FPGA designs, but not ASICs.
    if rst = '1' then
      cnt <= 0;
      valid_out <= '0';
    end if;
  end if;
end process;

p_label : process ( clk ) is
begin
  if rising_edge(clk) then
    if rst = '1' then
      cnt <= 0;
      valid_out <= '0';
    elsif valid_in = '1' then
      if cnt = 1 then
        valid_out <= '1';
      end if;
      cnt <= (cnt + 1) mod 2;
    else
      valid_out <= '0';
    end if;
    data_out <= data_in;
  end if;
end process;