signal change in VHDL

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alexz

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vhdl detect signal change

How to detect a std_logic_vector change?
I see I can not use the " 'change " attribute because it is not synthesizable.
 

vhdl signal change

what you can do is, delay the signal by 1 clock cycle and then perform XOR with delayed signal

let us assume that y be your std_logic_vector and f1_y be the delayed signal

detect_change <= f1_y XOR y;

whenever there is a change in y, there will be a pulse on detect_change

hope this will help...
 

process changing vhdl

here is a sample code...

PROCESS(clk, rst)
BEGIN
IF (rst = '1') THEN
f1_y <= (OTHERS => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
f1_y <= y;
END IF;
END PROCESS;

f1_y is delayed signal of y
 

vhdl delayed version of a signal

So, then I have to check weather f1_y = y in a different process right?
 

signal change vhdl

no you don't need to place it in a different process, which will make another clock cycle delay...

detect_change <= f1_y XOR y;
you can do this outside the process
 

vhdl change

put another process in ur programme like

process(anai)
c <= a and anai;
end process;

where anai is the logic vector u defined..and choose " a <= '1' "..observe c at the out put...
 

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