signal and variable in vhdl

[ahmadagha23]

Hi
what is the diffrence between signal and variable in vhdl at implementation ?(what are the hardware that signal and variable map to?)

and why the following program:

architecture var of test is
begin
process(clk)

variable c:std_logic_vector(0 to 7);
variable d:std_logic_vector(0 to 7);
begin
if clk='1' then
c:=a;
d:=c;
b<=d;
end if;
end process;
end var;
is faster than the following one after implementation?:

architecture sig of test is
signal clk:bit;
signal c,d:std_logic_vector(0 to 7);
begin
process(clk)
begin
if clk='1'then
c<=a;
d<=c;
b<=d;
end if;
end process;
end sig;

thanks

 

[delay]

Read this link and figure out your answer.

 

[desea]

Variable is used to describe your logic function. generally it doesn’t synthesized to hardware object.In a sequential process which has “clk” in it’s sensitive list. Signal is synthesized into D flip-flop.
Then let’s take a look at your two architectures.
The first architecture inferred one DFF, which connected ‘a’ as it’s D and ’b’ as it’s Q. variable c and variable d was canceled by synthesis tools.
The second architecture inferred three DFF.DFF1 has ‘a’ as its D, ’c’ as it’s Q; DFF2 has ‘c’ as D and ‘d’ as Q; DFF3 has ‘d’ as D and ‘b’ as its Q.
So, in your first architecture, signal b was set to the value of signal a after one clk. but in your second architecture, signal b was set to the value of signal b after three clk.

 

[cesardelahoz]

try this link, **broken link removed**

 

[bercam]

Hi ahmadagha23,

Main difference between signal and variable is at the moment when updating their values.

Variable-> This type is defined within a process block (not concurrently execution). Their value is updating when making proper assignment.

Signal -> This type can be defined out of process, any new event in signals is buffered and not updated until the end of execution of the running process.

 

[bibo1978]

Hi,
I dunno what do you mean with the fist code the first code is an example of bad coding style, you used two variables as a wires "meaningless" so the first code is merely a register but even though I think you must add if clk'event and clk ='1' "rising_edge" I never wrote if clk ='1' to do a register it seems confusing however it mightwork as clk is in the process sensitivity list but I am not sure of that, the second code might be a shift register "three registers wide shift register" if it was realized as if clk'event and clk ='1',
In general when dealing with variables one must be careful to assign the variable in all conditions of the process "else if or case condition or evena default value" else there might be a un-welcomed latches. Ibelieve you should read a HDL design book it is quite good

 

[bercam]

All variables involved in a process sentence and clk must be included in the sensivity list.

process(clk, var_a, var_b)
variable var_a, var_b :integer;
begin

if clk='1' then
a:=b
endif
end process

 

[cesardelahoz]

eemapi, you can find a lot of excelent vhdl tutorials in edaboard, search in the forums

 

[ydao]

All variables involved in a process sentence and clk must be included in the sensivity list...

are you sure?