Sign extension problem. Msb doesn't copy properly with a loop.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity sign_extend is
	port ( offset : in std_logic_vector ( 15 downto 0 ) ; 
			 offset_out : out std_logic_vector ( 31 downto 0 )  ;
			 msb_check : out std_logic 
		  ); 
end sign_extend;

architecture Behavioral of sign_extend is

	signal msb : std_logic; 
	signal temp: std_logic_vector ( 31 downto 0 ):= (others => '0') ;

begin 
	
	process (offset) 
	begin 
	
		msb <= offset (15); 
		temp ( 15 downto 0 ) <= offset ; 
		
		for i in 16 to 31  loop 
			temp (i) <= msb ; 
		end loop; 
	
	end process ; 
	
	msb_check <= msb ; 
	offset_out <= temp ;
	
end Behavioral;

--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   12:40:11 04/29/2014
-- Design Name:   
-- Module Name:   C:/Users/WORK/Desktop/MIPS PROCESSOR/COMPONENTS/sign_extend/tb.vhd
-- Project Name:  sign_extend
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: sign_extend
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY tb IS
END tb;
 
ARCHITECTURE behavior OF tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT sign_extend
    PORT(
         offset : IN  std_logic_vector(15 downto 0);
         offset_out : OUT  std_logic_vector(31 downto 0);
         msb_check : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal offset : std_logic_vector(15 downto 0) := (others => '0');

 	--Outputs
   signal offset_out : std_logic_vector(31 downto 0);
   signal msb_check : std_logic;
   -- No clocks detected in port list. Replace <clock> below with 
   -- appropriate port name 
 
--   constant <clock>_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: sign_extend PORT MAP (
          offset => offset,
          offset_out => offset_out,
          msb_check => msb_check
        );

   -- Clock process definitions
--   <clock>_process :process
--   begin
--		<clock> <= '0';
--		wait for <clock>_period/2;
--		<clock> <= '1';
--		wait for <clock>_period/2;
--   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	
		offset <= "1101010101010101" ; 
		
		wait for 100 ns ;
		offset <= "1100000000000000" ;
		
		wait for 100 ns ;
		offset <= "1111000000111100" ; 
		
		wait for 100 ns; 
		offset <= "1111111111111111" ; 
		
		wait for 100 ns ;
		offset <= "1011111100011110"; 
--      wait for <clock>_period*10;

      -- insert stimulus here 

      wait;
   end process;

END;