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sigma delta simulation question

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hi all,
i have design a sigma delta adc.
the fft results of both "matlab" and "veriloga" and "veriloga_sw & mos_amp" is fine.
if the veriloga sw be changed to cmos-sw,
the dc noise peak arise, & independent of fft point number.
the 1/R_sw/C_s ~= 6*(2*pi*f_sample).
my english is very poor,
thanks for your help!!

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