sigma delta converter and how to form an n-bit output?

[svensl]

I would like to know how the digital output (1-bit) from a sigma delta data converter can form an n-bit signal using decimation.

Thanks

 

[obi1]

to understad that you must read the basics of sigma-delta convertor; it`s all about noise shaping and filtering.

 

[vsgiri]

Hi svensl!

One method of implementation is an up/down counter + accumulator.

The up/down counter acts as a filter. Being triangular in time domain, it is sinc2 in freq domain.

The accumulator acc=acc+count if dig.o/p=1 else acc=acc

At the end of one up/down cycle the n-bit accumulator gives you the adc result!

You will have to play around with the decimation period - the up/down counter clock - the no.of bits etc.

Hope this helped.

Giri

 

[svensl]

Thanks for your response Giri. I am not entirely certain if I understood you correctly. If I take the 1bit output stream (0,1) from a SD modulator and decimate the signal with a sinc decimator, I average let's say 4 samples and divide by 4 before dumping the result to the output. So as an example if I have 0101010 then
using a moving average filter I average the first 4 sample 0101=2/4, then move one over and average the next 4 samples 1010=2/4, 0101=2/4 and finally the last four 1010=2/4. I will have 4 numbers 0.5,0.5,0.5,0.5. But how does this represent a 2 bit number, meaning how to get a binary number xxxx.

s

 

[vsgiri]

Ok. Suppose u want a 4 bit ADC o/p(binary), make a 2 bit up/down counter. (This method I believe is the simplest)

Suppose your signal is in the 50% range, so you get 0101010...

start with acc=counter=0

clock 1 : count=0 acc=0(here SD o/p=0)
clock 2 : count=1 acc=1(because SD o/p=1)
clock 3: count=2 acc=1(sd=0 here)
clock 4: count=3 acc=4(sd=1 here)
clock 5: count=2 acc=4
clock 6: count=1 acc=5
clock 7:count=0 acc=5 : 0101

If your SD mod gives all ones your acc o/p would be 9

And all zeros would give zero


So your full scale value is 9 for a 2-bit counter
Your acc value will be relative to this full scale value of 9.

If you have a large counter the 1 lsb error we get here will vanish.

I hope it is much clearer now

Giri

 

[svensl]

Thanks for the clarification. I do know how it works now. In the example you gave you would decimate by 7 since you consider (average) seven 1-bit outputs from the SDM. Can you give further references on different implementation schemes, if you have them handy by any chance?

Thanks.