SiGe BiCMOS HBT npn layout

[prcken]

Hi

In IBM8HP SiGe BiCMOS process, the npn has 4-terminal in the schematic symbol, while the layout only shows 3-terminal, there is no bulk.

How should I connect the bulk (always ground?) in the schematic and just add a P-Sub as a bulk in the layout?　



Thanks!

 

[D.A.(Tony)Stewart]

YOu may need an NDA to get design details

https://www.mosis.com/pages/design/kits/vendor-kits-menu

 

[prcken]

Yes, I have NDA. But I couldn't find a document (I've checked training manual and design manual) talked about this for the timing being.
You meant ask MOSIS directly?
Thanks!

 

[Dominik Przyborowski]

Make a ring around tranistor to the substrate.

 

[prcken]

Make a ring around tranistor to the substrate.

Thank you buddy I will try tomorrow, I think it also need a subc to pass LVS, right?
you are always helpful, last time helped a lot for the triple well nfet...

 

[Dominik Przyborowski]

I'm not sure because i never works with BiCMOS but it's most probably what You should do (contact to substrate at layout and subc between gnd! and 4th terminal).

 

[dick_freebird]

The subc is probably implicitly netlisted (there will be some psub
connectivity everywhere, in a P-handle JI technology). Depending
on what the collector is doing, you may not want the local psub
connection to be very low impedance - series R reduces the
undesirable Ccs' high frequency "effectiveness". You might want
to investigate the impact of low and high series resistance to
the below-collector substrate if you're looking for maximum RF
bandwidth / gain@freq, and if it's shown to matter than you
know you want to take care with your modeling and physical
design.

 

[prcken]

I passed DRC, LVS and PEX with an npn device today. Just get familiar with the run set flow.
here is my schematic and layout view


Here is one issue left as shown below after i generated the calibre view after running PEX


Zoom-in


- - - Updated - - -

The subc is probably implicitly netlisted (there will be some psub
connectivity everywhere, in a P-handle JI technology). Depending
on what the collector is doing, you may not want the local psub
connection to be very low impedance - series R reduces the
undesirable Ccs' high frequency "effectiveness". You might want
to investigate the impact of low and high series resistance to
the below-collector substrate if you're looking for maximum RF
bandwidth / gain@freq, and if it's shown to matter than you
know you want to take care with your modeling and physical
design.

you are quite right.
And it also used to bias substrete to Vss or GND, prevent latch-up, isolate some circuits.