Should i synthesis again if time constrain is wrong

[BigJJ]

For example, i synthesized some module with 1GHz time constrain and there was no negative slack.

So, I did PnR also with 1GHz time constrain and there was negative slack.

In this case... should I synthesized module again with lower frequency? or it is enough just changing PnR time constrain?

 

[dpaul]

In this case... should I synthesized module again with lower frequency?
In most cases the clock is fixed to a value during design definition phase and cannot be changed. But if you have the liberty to chnage then go ahead. It would be the easiest solution.

or it is enough just changing PnR time constrain?
If the clock is fixed, then you need to revise your design constraints file. In many cases pipelining the design also helps.

 

[BigJJ]

In this case... should I synthesized module again with lower frequency?
In most cases the clock is fixed to a value during design definition phase and cannot be changed. But if you have the liberty to chnage then go ahead. It would be the easiest solution.

or it is enough just changing PnR time constrain?
If the clock is fixed, then you need to revise your design constraints file. In many cases pipelining the design also helps.

First of all, thanks for your help.

If you don't mind can i ask question with more detail..?

My module is single cycle crossbar. The crossbar's max operate frequency are rapidly decrease when the number of in/output port of crossbar increase. I want to show above crossbar property myself.

So, for example, i made 5x5, 10x10, 20x20 crossbar verilog.

Then to figure out max frequency, i first picked 5x5 crossbar and synthesized again and again increasing frequency until occur a few of negative slack. And the max frequency of 5x5 was 1GHz.

After synthesis, i do the PnR the 5x5 crossbar wit 1GHz time constrain. But the PnR fail to meet 1GHz frequency and occur many negative slack.

Then i should synthesis with lower frequency like 800MHz again then do PnR? Are there some different synthesis result with 1GHz and synthesis result with 800MHz?

I mean... i don't need to meet some frequency.. i just want to get some kind of tendency(?)

 

[ThisIsNotSam]

this is a classical issue of mismatch between logic synthesis and physical synthesis. it is not specific to your design or technology. many workarounds exist: you can perform logic synthesis that is layout/floorplan-aware. you can overconstrain logic synthesis. you can let physical synthesis use lvt cells, while logic synthesis uses only svt/hvt. ...