Shoot-through avoidance technique in synchronous boost converter is dubious?

Page 12 (LHS) of the following datasheet (below) says that the source of the lower fet in the synchronous boost should be tied to –2V so that it doesn’t get induced ON when the top (synchronous) fet turns ON. (it says that this is how shoot-through is avoided)
Surely this is not correct?
I mean, by the time the top (synchronous) fet turns on, the drain voltage has already risen to vout + v(diode).
By ”v(diode)”, I am referring to the schottky diode that goes from drain to source of the top fet.

LTC3813 (synchronous boost controller) Datasheet:-
http://cds.linear.com/docs/en/datasheet/3813fb.pdf

Do you agree that there is no shoot-through problem between top and bottom fets since the top fet is never turned on when the bottom fet is on, and there is no shoot-through when the top fet turns on either?

treez said:

Page 12 (LHS) of the following datasheet (below) says that the source of the lower fet in the synchronous boost should be tied to –2V so that it doesn’t get induced ON when the top (synchronous) fet turns ON. (it says that this is how shoot-through is avoided)
Surely this is not correct?

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You're right, that's not correct. The datasheet doesn't say that at all:

To prevent this from occurring,
the bottom driver return is brought out as a separate pin
(BGRTN) so that a negative supply can be used to reduce
the effect of the Miller pull-up.

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This means the gate drive to the lower FET is made bipolar, which is indeed a valid way to avoid shoot through and oscillation.

Thanks, but shoot through would be when both fets are on together, and this can never happen, even if the drive to the bottom fet is unipolar...surely you agree?
I have viewed datasheets of thousands of pwm controller IC's , and this is the first one ever that suggests a bipolar drive for the bottom fet in an smps.
I believe this is unnecessary (ie the bipolar drive for the bottom fet).
Surely you agree?
If they worry about unwanted transient rise on the bottom gate, then they should be specifying that the bottom fet is never of the logic threshold type.

I mean, surely its bizarre, I mean, all hard-switched smps's have a high dv/dt on the drain node....but one is never told that you need a bipolar bottom fet drive in order to combat it....(except for the above LTC3813 Datasheet)

Your post involves two questions:

Firstly how's the shoot-thru protection means working which has been clarified by mtwieg.

Secondly why could it be necessary. You're apparently assuming, that commutation from low-side to high-side switch always occurs passively and the high-side transistor is conducting after schottky diode. Why?

I don't see any waveforms in the datasheet specifying the control signal sequence. It may be that active low-to-high communation with minimal dead-time turns out more effective for high switching frequency.

Secondly why could it be necessary. You're apparently assuming, that commutation from low-side to high-side switch always occurs passively and the high-side transistor is conducting after schottky diode. Why?

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well, because there should be dead time between the bottom fet going off and the top fet coming on.....to avoid shoot-thru. Also, the dead time allows the schottky to conduct which is wanted because you never want the upper fets internal diode to start conducting as it may well have a big reverse recovery...the schottky shorts out the upper fets internal diode.

I believe that you are basically guessing, partly unsubstantiated. E.g. how should activating the high-side transistor early cause conduction of its substrate diode? The opposite is true.

I keep the point that we don't know how the gate signal sequence is exactly timed. Guessing how it "should be" isn't particularly fruitful. A problem in design process might be to determine if negative BGRTN bias should be implemented or not, because it usually involves an additional negative supply. It's declared optional, so it's probably not required under standard conditions.

ok thanks, I see your point, as you know, the route of this conversation is shoot-thru of the fets.
You are quite rightly saying that maybe there is insufficient dead time between top and bottom fets.....I will check this on the simulator....I would be very surprised if this company haven't added sufficient dead time in there, I know they do put it in with their LT8705 chip, and incidentally, the datasheet for LT8705 makes no mention of the need for a negative lower gate drive even though LT8705 acts as a synchronous boost.

There must be loads of ICs that manage hard switched topologies where there is a top and bottom fet with dead time, (eg full bridge, half bridge, sync buck) and none say a negative lower fet gate drive is needed. I've seen it with IGBT INverters, but that's because of the tail current noted with IGBTs. I have never seen a FET based, hard switched SMPS with a negative fet drive, and I have worked in more than 10 SMPS companies, including global names that all will have heard of.

I have never seen a FET based, hard switched SMPS with a negative fet drive, and I have worked in more than 10 SMPS companies, including global names that all will have heard of.

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I agree that negative gate voltage for MOSFETs is very unusual, normally not needed and thus avoided for design economy reasons. It's nevertheless an option.

The datasheet refers to shoot through that happens to dv/dt induced turn on due via miller capacitance, as opposed to shoot through resulting from overlapping outputs from the gate driver. When the upper FET turns on, the lower FET's Qgd must be charged, and the Qgd must flow towards the gate. If the impedance looking back toward the gate driver is high enough, and the charge transfer happens fast enough, the Vgs of the lower FET may rise substantially. In theory if the Qgd of the lower fet is at least as much as its Qgs (the charge required to raise the gate voltage from zero to Vth), then the lower FET may conduct, and you get cross conduction. This happens completely independent of the dead time applied by the drivers.

Sometimes the miller charge ratio of the FETs is selected to make this impossible. Otherwise using a negative drive voltage is effective, since it basically causes Qgs to increase.

When the upper FET turns on, the lower FET's Qgd must be charged

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When the upper fet turns on, the Qgd of the lower fet is already completely charged, because when the upper fet is turned on, the schottky across it has already started conducting, and the drain node is at v(out)+v(diode)

.....As such, by the time the top fet is being switched on, the bottom fet's gate has long gone through its miller region. Also, when the top fet turns on, the bottom fet has Vds(off) across it, and so its DS capacitance (and DG capacitance) is small. There is no miller charging going on in the bottom fet when the top fet turns on.

I think you are referring to operation without a parallel schottky across the top fet?....I must confess that I always operate synchronous boost with a schottky across the top fet....and this was always done in a global lighting company that I worked at........since the top fet is turned on when its DS voltage has already been shorted by the schottky to 0.5V...the top fet gate driver sees no miller charge region I am sure you agree with this.......the top fet only has to turn off quickly, it doesn't have to turn on quickly as the turn-on switching losses for the top fet are minimal since its already been shorted by the parallel schottky.........If we are worried by a rapidly rising gate voltage of the top fet, then we should use a diode and resistor there so that the top fet turns on (relatively) slowly and turns off quickly....I realise that you may agree with this point, as we didn't discuss it before.

Mtwieg's explanation is spot on, and there is not much else I can add.
My two cents is as follows: Linear Technology is a performance oriented company. They may have observed in certain applications or with a particular component set, that there was some efficiency loss due to Miller-induced shoot thru.

They may have decided that -for those customers requiring that- including the option of using negative bias for the bottom mosfet would help towards their efficiency goal.

If your circuit may trade off the small efficiency penalty for lower cost, then tie that pin to ground.

if you are saying that there is miller induced shoot through, then that is saying that whilst the bottom fet turns off, then as the bottom gate voltage transitions up through the miller region, the bottom fet then turns itself back on. This happens before the top fet is even starting to be turned on.
That's what "miller induced shoot through " would have to mean.
It isn't likely.

(BTW I also think linear.com is an excellent company, and have a full SMPS course written with ltspice simulations to demo every point.)

treez said:

When the upper fet turns on, the Qgd of the lower fet is already completely charged, because when the upper fet is turned on, the schottky across it has already started conducting, and the drain node is at v(out)+v(diode)

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Maybe, but that's not the point. The point is the fast rise in Vds of the lower FET (whether by commutation of the upper FET or its diode) pushes charge onto the gate of the lower FET. In principle this type of cross conduction can happen even when there is no current forcing commutation of either diode. You can see it with a simple half bridge circuit with nothing connected to the output, under the right conditions. For a simple example, try simulating an old FET like an IRF510 with a 1k gate pulldown resistor, then drive its drain with a 50V pulse with a 200ns rise time. You will see conduction due to miller charge alone. Then change the gate bias voltage to -10V, and the cross conduction should be decreased greatly.

schmitt trigger said:

My two cents is as follows: Linear Technology is a performance oriented company. They may have observed in certain applications or with a particular component set, that there was some efficiency loss due to Miller-induced shoot thru.

They may have decided that -for those customers requiring that- including the option of using negative bias for the bottom mosfet would help towards their efficiency goal.

If your circuit may trade off the small efficiency penalty for lower cost, then tie that pin to ground.

Click to expand...

Agreed, Linear loves to put in neat features that are usually not needed (and sometimes very annoying). I'm certain this feature is rarely used in practice.

The point is the fast rise in Vds of the lower FET (whether by commutation of the upper FET or its diode)

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..I am sure you appreciate that the fast rise of the vds of the lower fet is due to the turn off of the lower fet, and then the charging up of the bottom fet capacitances by the inductor current, which must keep flowing when the fet turns off.

treez said:

..I am sure you appreciate that the fast rise of the vds of the lower fet is due to the turn off of the lower fet, and then the charging up of the bottom fet capacitances by the inductor current, which must keep flowing when the fet turns off.

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In a typical boost circuit, yes, this is what happens. But what exactly causes the rise in Vds isn't relevant to the purpose of the bipolar drive.

Also just to make sure readers don't get confused, this is not the same failure mechanism that happens when the internal BJT in a power FET is activated, which is another dv/dt related problem.

I feel that some considerations in this discussion are a bit theoretical. Miller-capacitance induced turn-on of the low side transistor is only likely to happen (if at all) if the high-side transistor is turned on agressively (early and with large gate current). With passive commutation, controlled by inductor current and transistor output capacitance and realistic gate driver impedances, it's about to impossible.

Usually it can be savely avoided by making the gate driver currents asymmetrical.

If the discussed boost converter performs early turn-on of the high-side transistor or relies on passive commutation isn't obvious from the datasheet information.

FvM said:

I feel that some considerations in this discussion are a bit theoretical. Miller-capacitance induced turn-on of the low side transistor is only likely to happen (if at all) if the high-side transistor is turned on agressively (early and with large gate current). With passive commutation, controlled by inductor current and transistor output capacitance and realistic gate driver impedances, it's about to impossible.

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Right, it usually manifests in the classic plateau in the gate voltage of the lower FET, which slows down its turn off and increases switching losses. But that isn't cross conduction. I think in theory it is possible for a true sustained oscillation to develop here, but in practice I've never seen it.

If the discussed boost converter performs early turn-on of the high-side transistor or relies on passive commutation isn't obvious from the datasheet information.

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Exactly. Knowing Linear, they may be pushing the dead time down very far. But keep in mind, under light load conditions the "passive" commutation may be slow enough that the "active" commutation comes into play and some cross conduction may occur.

When I write to linear.com about things, they often direct me to try it on the simulator, so here it is on the simulator, (but unfortunately it is "ticking")
If any reader knows what is causing this ticking then please let us know, then we can see if we can simulate this problem of shoot through conduction which the datasheet warns us about...or at least I will anyway.
(LTspice simulator is free download from linear.com)

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ok simulation sorted now, ITH pin misconnection.
Don't see any sign of the shoot through, even with some gate stray inductance, but will try at light load as per kind advice.

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Here is the LTC3813 simulation at light load ....there is no sign off the shoot through, ive tried putting in parasitics and never see it.

You probably won't be able to see it in such a simulation, at least not without intentionally forcing it to happen. Simply increasing the gate drive impedance will just increase switching times as described above, but probably won't cause cross conduction. However if you then put a negative bias on BGRTN you should see faster switching times and maybe higher efficiency.

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Actually I tried it myself and was able to observe it by increasing the gate resistor to 15 ohms. During the miller plateau on the bottom FET, the top FET is turned on and significant spike in the bottom FET's Vgs is seen, accompanied by a very large cross conduction current pulse in both FETs. Putting a -5V bias on BGRTN almost completely eliminates it. But the actual power lost is probably not worth the effort.

Actually I tried it myself and was able to observe it by increasing the gate resistor to 15 ohms. During the miller plateau on the bottom FET, the top FET is turned on and significant spike in the bottom FET's Vgs is seen, accompanied by a very large cross conduction current pulse in both FETs.

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Sounds plausible. But only achieved with resistor dimensioning far-off reasonable values.