shift register -- hold time violation?

[jerry2007]

hold time violation fix

I know clock should run reversely to avoid hold time problems for shift registers. But where/how should it be done in a standard design flow (We are using Cadence tools here)? My best guess is in the sdc file but I have no idea how to tell the tool about it... Thanks!

 

[au_sun]

fix hold time violation

Do u face any hold time violations in the shift registers after P&R ?

 

[avimit]

shift register hold time violation

I know clock should run reversely to avoid hold time problems for shift registers

1. I dont think so, or may be I haven't uderstood what you want to do. 'running clock reversely' what exactly you mean by that, do you plan to use both edges of the clock?

2. Well, shift registers are prone to hold problems, but pnr tools or synthesis tools are smart enough to put buffers in between the data path from one register to the other, so that there are no hold problems.

So I guess you dont have to worry abt hold problems in shift registers any more.
Kr,
Avi
http://www.vlsiip.com

 

[jerry2007]

synthesis hold timing violation

I am pretty sure it's a hold time violation because when I manaully connect the clk of one shift reg (say clk1 of reg1, which seems to have racing problems) to its neighbouring shift reg clk (clk2 of reg2, clk1 and clk2 are leaf nodes in the same clk tree) I can observe racing at reg2 too, which I guess it's because the extra load slows down clk2, resulting in racing at reg2.

By 'reversing clk' i meant always making sure that clk to shift regs at later stages are earlier than shift regs at earlier stages. thus avoiding racing. But inverting buffers is definitely a good alternative. What's strange is that the backend tool Encounter didn't insert any buffer between shift regs, even when I give extremely stringent clk uncertainty constraint in sdc. Is there a way to explicitly guide the tool to do that, or is it safe to just add buffers manually in the netlist right after the front end (which doesn't sound very appealing...) Thanks again!

 

[avimit]

shift register layout clock

I am surprized why the tool has not inserted buffers. The thing is, I am a Front End engineer, and my domain ends where I synthesize design, and produce a good looking netlsit. So I am sorry on this occasion, I wont be able to help you with your PnR tools. The only thing which I know is if the area in which you want to do the placement is less, then the tool might not be able to put in hold buffers, no matter wot your sdc constraints are.
Kr,
Avi

 

[stormwolf]

timing violations -- backend synthesis

You may set two clock , so synthesis tools think there two clock aren't sync clock. You should use generate clock to set those two clock , and synthesis tools think those two clock is sync, synthesis tools will insert cell auto.

 

[jerry2007]

hold time for shift register

to avimit: I intentionally gave a pretty large floorplan to make density less than 50% but still, no buffers inserted. I manually inserted some buffers in the post-layout netlist and the simulation worked fine (but this won't help the layout/routing) Thus right now I am actually thinking about manually inserting buffers in the pre-layout netlist and then set_dont_touch to prevent them being optimized away. But this is really awkward because I will have to decide how many buffers and what kind of buffers to insert myself.

to stormwolf: could you explain some more? I do have two clocks in the design and I did use create_generate_clock but how is this related to the shift regs (which all use the same clk)?

 

[Thinkie]

sdc +hold time violation

hmmm... if your constraints are right then some buffers should be inserted automatically. Registers connected back-to-back are prone to hold violations.

My guess is to check your contraints first in case something prevents buffers from being inserted.
Then try to place manually buffers on your netlist.

 

[stormwolf]

hold violation shift register

I think you mean shift reg is for SCAN-DFF. When you do synthesis,
1. if between two clock domain , it will insert a latch to fix the data delay time.
2. And at shift scan chain , some hold time violation , synthesis tools can't deal with it, fix hold timing isn't synthesis work, and those will be fixed at backend.

Added after 17 minutes:

When we do a project , scan chain has a hold timing violation. Scan Cell working in same clock,
we will insert delay cell at backend. When do scan insert , synthesis tools just connect shift register, it will not optimaize timing of shift chain.

 

[jerry2007]

back to back register hold time

in fact this shift reg wasn't for scan. there are other shift regs in my design but they didn't have any hold time problem (that's what puzzled me). Nontheless, i just don't know how to explicitly guide the tool (in this case, encounter) to insert delay cells/buffers for it. so how is the delay cells in your designs inserted? is it added automatically by the tool? Thanks!

 

[xuanzhu]

how to avoid hold time violations

if this is a critical issue, you can change your mind : use the reverse clock to drive a group of temporary dffs, therefore your design can run a higher frequency.Use the folloing structure
posreg (.d(din), .q(q[0]);
negreg (.d(q[0], .q(temp[0]);
posreg (.d(temp[0], q[1]);
..........
negreg (.d(q[n-1], .q(temp[n-1]);
posreg (.d[temp[n-1], .q(q[n]);

 

[stormwolf]

negative timing check limit not allowed

When you run a synthesis tools, usally synthesis tools just analysis setup timing and some holdup timing, If encounter doesn't report the hold timing
violation , then encounter didn't analyse the hold timing, if the tools don't know the violation, it can't fix it. If synthesis tools report it , you just need to
resynthesis it to fix.
And we usally to deal with the question is:
1. synthesis to optimize
2. insert by manual
3, backend to fix it
And you may mean use some command to insert a delay cell between the shift register , but i can't find the command .

 

[jerry2007]

So I changed the set_clock_uncertainty -hold to a very small value and back-annotation looks correct, but still no buffers inserted in the netlist. I guess what reducing 'uncertainty' did was to balance the clock tree better by inserting more buffers (correct me if I am wrong here). Still doesn't seem to be the solution.

I also double checked the sdc and didn't find anything potentially disabling buffer insertion. I also noticed the hold time constraint in .lib/.v is negative (and a warning during design elaboration: negative timing check limit not allowed in a 1 limit timing check), so maybe that's why encounter never caught a violation?

I also tried inserting negreg or buffers after frontend synthesis, and both worked, but I feel this is really bad for flow automation...