shift operator in vhdl

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Junus2012

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Dear friends

I am trying to use the shift operation to implement ring counter in vhdl, but always the simulator showing me error about using the ror

this is my code and I look for your help

Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.numeric_std.all;


---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity roror is
    Port ( clk : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           q : out  STD_LOGIC_VECTOR (3 downto 0));
end roror;

architecture Behavioral of roror is

signal a : std_logic_vector (3 downto 0);
signal b : std_logic_vector (3 downto 0);

begin

a<= "1000";
process (clk, rst)
begin

if (clk' event and clk = '1')then
b <= a ror 3;

end if;
end process;
q <= b; 


end Behavioral;
 

Just before you start posting about the next error about signed/unsigned types not being visible, you need to remove the std_logic_arith library from your code.
 
thanx, again its not working, nd i think keeping the library is not gonna changing thing to error

TrickyDicky said:
Just before you start posting about the next error about signed/unsigned types not being visible, you need to remove the std_logic_arith library from your code.
Click to expand...
 

Well, you didnt post the new code or the error, so we cannot help.

But you need to delete the library. numeric_std and std_logic_arith have clashes. std_logic_arith is non-standard and numeric_std should be used instead.
 
Besides using possibly conflicting libraries, you didn't check at all which libraries define "ror" for which data types.

ror is defined in ieee.numeric_std, for unsigned and signed type only. It's not defined in the legacy synopsis libraries or ieee.std_1164. So it's pretty clear why ror can't work in your code.

ieee.numeric_std has however xror working for std_logic_vector.

And needless to say that you can easily write your own rotate operation for std_logic_vector.
 
Dear FvM

as I understood from u there are some conflecting libraries. I can remove any of the libraries which i post cause I need them for the rest of my task, I am not intending to use the code to do only rotate (ROR). I will use some other arithmetic and logical operations.
if you say that I do ror by myself, what about if i need further shifter operations, rol,ssl ...etc,,, you do it all by yourself ??

thank you once again FvM


- - - Updated - - -

hello

this is the error message

"ror can not have such operands in this context"

TrickyDicky said:
Well, you didnt post the new code or the error, so we cannot help.

But you need to delete the library. numeric_std and std_logic_arith have clashes. std_logic_arith is non-standard and numeric_std should be used instead.
Click to expand...
 

Take a look at **broken link removed**

ieee.numeric_std has the following functions you can use with signed or unsigned (a std_logic_vector would have to be converted first to be used with these)

Code VHDL - [expand]
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--============================================================================
  -- Shift and Rotate Functions
  --============================================================================
 
  -- Id: S.1
  function SHIFT_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
  -- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
  -- Result: Performs a shift-left on an UNSIGNED vector COUNT times.
  --         The vacated positions are filled with '0'.
  --         The COUNT leftmost elements are lost.
 
  -- Id: S.2
  function SHIFT_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
  -- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
  -- Result: Performs a shift-right on an UNSIGNED vector COUNT times.
  --         The vacated positions are filled with '0'.
  --         The COUNT rightmost elements are lost.
 
  -- Id: S.3
  function SHIFT_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
  -- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
  -- Result: Performs a shift-left on a SIGNED vector COUNT times.
  --         The vacated positions are filled with '0'.
  --         The COUNT leftmost elements are lost.
 
  -- Id: S.4
  function SHIFT_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
  -- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
  -- Result: Performs a shift-right on a SIGNED vector COUNT times.
  --         The vacated positions are filled with the leftmost
  --         element, ARG'LEFT. The COUNT rightmost elements are lost.
 
  --============================================================================
 
  -- Id: S.5
  function ROTATE_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
  -- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
  -- Result: Performs a rotate-left of an UNSIGNED vector COUNT times.
 
  -- Id: S.6
  function ROTATE_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
  -- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
  -- Result: Performs a rotate-right of an UNSIGNED vector COUNT times.
 
  -- Id: S.7
  function ROTATE_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
  -- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
  -- Result: Performs a logical rotate-left of a SIGNED
  --         vector COUNT times.
 
  -- Id: S.8
  function ROTATE_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
  -- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
  -- Result: Performs a logical rotate-right of a SIGNED
  --         vector COUNT times.
 

If you use numeric_std there is absolutly no need for std_logic_arith. If you find something you can only do with std_logic_arith, please let me, and the world, know about it.

You are going to make your life way easier if you just use the shift functions out of the numeric_std package.
 
thank you friends all very much for your kind help
I solved the problem now,
I use manually the shift operation , thats better, then i put them in a package and I reuse it whenever i want and keeping using standard data types.

if you also interest, I have cut this page from book of " circuit design and simulation with vhdl" by pedroni
 

Attachments

  • Circuit Design and Simulation with VHDL.pdf
    60.3 KB · Views: 184

hello

I used the function to put the ROR there

Code: 
function rotate_right (signal d_in:std_logic_vector)return std_logic_vector is


variable b : std_logic_vector (d_in' range);

begin

b := (d_in' low & d_in(d_in' high downto d_in low+1));

return b;

end rotate_right;

but I am getting this error

" parse error, unexpected IDENTIFIER, expecting CLOSEPAR" which point at the b equation,

Im unable to find the reason, please
 

That's because din'low is an integer, not a std logic. You need din(din'low).

btw, this function is has an error. If din is declared (0 to n) it will throw an error because you accessed it using down to. You need to check the direction of the array inside the function.

much better to use the existing functions rather than reinventing the wheel.
 

These two expressions are equivalent (using numeric_std)

Code: 
b := std_logic_vector(unsigned(d_in) ror 1);
b := std_logic_vector(rotate_right(unsigned(d_in),1));
 
Thank you FvM so much

I used your code and its working fine

what about my function, as a second solution what the problem it has ??

thnaks

FvM said:
These two expressions are equivalent (using numeric_std)

Code: 
b := std_logic_vector(unsigned(d_in) ror 1);
b := std_logic_vector(rotate_right(unsigned(d_in),1));
Click to expand...
 

Junus2012 said:
what about my function, as a second solution what the problem it has ??

thnaks
Click to expand...

i gave you the solution. You are not indexing into the array for the first bit.
 

Code: 
function rotate_right (signal d_in:std_logic_vector)return std_logic_vector is
  variable b : std_logic_vector(d_in'length-1 downto 0);
begin
  b := d_in;  -- this normalizes the range
  return b(0) & b(b'high downto 1);
end rotate_right;

It is important to normalize the inputs to a function. This is because you might have f("0101011") or f(x(5 downto 2)) at some point. VHDL defines vectors as 0 to N-1 by default, so "0101011" is 0 to 6. Likewise there is no 0 element for x(5 downto 0).
 
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