cupoftea
Advanced Member level 6
Hi,
We are doing 4-layer 60W BuckBoost with Vin = 10-30V to vout = 5v to 20V
Fsw = 420kHz.
The enclosure is very tight, we had to have the power inductor on the opposite side
of the board to some sensitive digital signals which affect the SMPS operation.
Also, the inductor overlaps some of the SMPS control chip.
However, there was no choice in this due to space constraint.
We do have on layer 2, just under the inductor, a pretty solid ground plane which we hope will shield the switching node from the sensitive signals. However, the SMPS is working
intermittently, sometimes works, sometimes doesnt.
We cant adjust the FET drain rise/fall time as all 4 fets and their drives, are inside the chip. Only the inductor and an output current sense resistor is outside the chip.
Do you think a thin layer of internal plane copper is enough to shield the switching node
from sensitive signals? The SMPS controller is especially sensitive as it contains
a charger controller micro aswell.
Pretty much the entire power stage and input/output caps are on a 4-layer board which is some 20mm by 20mm.
The digital signals which go into the chip set its vout. Part of the noise operation we are seeing is that the vout of
the chip changes from regulated 20v (say), to regulated 5V....as if noise has somehow got into the digital
signal lines. This often happens as we manually raise reduce the load resistance (increase i(out).
We are doing 4-layer 60W BuckBoost with Vin = 10-30V to vout = 5v to 20V
Fsw = 420kHz.
The enclosure is very tight, we had to have the power inductor on the opposite side
of the board to some sensitive digital signals which affect the SMPS operation.
Also, the inductor overlaps some of the SMPS control chip.
However, there was no choice in this due to space constraint.
We do have on layer 2, just under the inductor, a pretty solid ground plane which we hope will shield the switching node from the sensitive signals. However, the SMPS is working
intermittently, sometimes works, sometimes doesnt.
We cant adjust the FET drain rise/fall time as all 4 fets and their drives, are inside the chip. Only the inductor and an output current sense resistor is outside the chip.
Do you think a thin layer of internal plane copper is enough to shield the switching node
from sensitive signals? The SMPS controller is especially sensitive as it contains
a charger controller micro aswell.
Pretty much the entire power stage and input/output caps are on a 4-layer board which is some 20mm by 20mm.
The digital signals which go into the chip set its vout. Part of the noise operation we are seeing is that the vout of
the chip changes from regulated 20v (say), to regulated 5V....as if noise has somehow got into the digital
signal lines. This often happens as we manually raise reduce the load resistance (increase i(out).