Hi all,
I need some code to share I2C EEPROM between 2 PIC. I need to use multi-master configuration. The first Master will write on the EEPROM and the second will read from. I need your help! (I use assembler)
I also not done it ever but I have an idea that you can not use two master at a time for this project or you can use one master and the second master as a slave and when you reqire data slave will put a request to master to do so.
Hi all,
I need some code to share I2C EEPROM between 2 PIC. I need to use multi-master configuration. The first Master will write on the EEPROM and the second will read from. I need your help! (I use assembler)
Hi,
I am also trying to to do the same with 2 pics and 1 eeprom.There is an application note in Microchips website.Try to read that one.I dont think its big problem to handle 2 masters in I2C.First setup MCU1 and MCU2 in master mode.ie you have to write the same code into both pics.
For starting communication each master must ensure that the bus is free.
Suppose MCU1 is communicating with eeprom,then MCU2 want to communicate to the same eeprom.MCU2 will send the start condition as usual.But only one of the msater will be able to hold the bus.Ie I2C bus line is a wired AND logic.So if a HIGH and LOW comes in the SDA line at the same time the result will be LOW in SDA line (1 & 0=0).So the master which transmitted the low will hold the bus (at any time during bit transmission)and can communicate to the eeprom.The other master will wait till the STOP is generated by the master which is communicating now.
Read the application 578b.pdf and you will get what you want to do?
One question from me.......Suppose 2masters are communicating to aa eeprom at the same time,with same data..then what happens?..As far as I could understat is that the data will be written to eeprom successfully...right?
Regards....
You dont need to worry about the difference in clock speeds in both MCUs,because the wired AND logic will correct the difference in clocks in both MCU during communication.(Read clock stretching in I2C).