iamxo
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adc on verilog
I use Diff-opamp with low rout ( while not OTA ) in spectre (using verilog-A) to construct the sample-hold amplifier for ideal pipeline ADC simulation, But I found that with this low rout Opamp, I had to set large opamp gain and GBW to obtain the desired snr/sndr. That is to say, when the gain and GBW is set to the value suitable for a certain ADC resolution ( for example, 8bit, the snr I get is only 32dB), the result is worse.
So, my query is whether the OTA is the main cause of the lower snr or not. should I model the SHA using OTA with high output impedance ?
Thank you very much
I use Diff-opamp with low rout ( while not OTA ) in spectre (using verilog-A) to construct the sample-hold amplifier for ideal pipeline ADC simulation, But I found that with this low rout Opamp, I had to set large opamp gain and GBW to obtain the desired snr/sndr. That is to say, when the gain and GBW is set to the value suitable for a certain ADC resolution ( for example, 8bit, the snr I get is only 32dB), the result is worse.
So, my query is whether the OTA is the main cause of the lower snr or not. should I model the SHA using OTA with high output impedance ?
Thank you very much