hebu
Full Member level 4
1)Non-overlapping clock.
How long we have to design the time gap between two phases. For example,
the clock frequency is 1MHz, how about 3nS time gap? it's enough?
2)The common mode bias to switch
Can we only use resistor divider to generate a voltage to bias the common mode
node of switch? or, we need to make a low impedance to the cm node such as
a unity gain buffer?
3)May I cascade any filter I want? For example, I design a band pass filter, may
I cascade a high pass filter and a low pass filter?
Thanks,
How long we have to design the time gap between two phases. For example,
the clock frequency is 1MHz, how about 3nS time gap? it's enough?
2)The common mode bias to switch
Can we only use resistor divider to generate a voltage to bias the common mode
node of switch? or, we need to make a low impedance to the cm node such as
a unity gain buffer?
3)May I cascade any filter I want? For example, I design a band pass filter, may
I cascade a high pass filter and a low pass filter?
Thanks,
