Several questions about the I2C-bus protocol

[McShamrock]

I would like to solve some questions about the I2C-bus protocol:

1. The arbitration mechanism is well described in specification (version 2.1) given by Philips. However, no information is given in case of arbitration between a transmitter and a receiver master device. I suppose the arbitration is first made on the 7 address bits of slave. In the worst case of addresses equal to each other, the arbitration is wined by the writing master, i.e. 8th bit = LOW. Is it correct?

2. Is even the arbitration taking place through the same wired-AND mechanism used by synchronization on SCL line?

3. Is the synchronization process taking place only during the arbitration (and just later the acknowledge bit in order the slave can tell the master to wait before transmitting again as a handshake mechanism)?

4. Is the synchronization process continuing until the end of the byte after a master understands it lost arbitration?

5. Is it possible the occurring of two different clock signals with equal frequency and opposite phase during the synchronization process? I suppose it is not, since the SCL line is HIGH when not used yet, and then both the two clock signals begin from HIGH position: they cannot have opposite phases since their phase shifting is at maximum equal to the START condition’s fall time, which is shorter than the minimum SCL clock period.

6. If a general call address is sent on the SDA line, every device requiring data from a general call address should reply by sending an acknowledge. How can several devices send acknowledge all together in the slot time of a bit only? As during synchronization process occurs, is it performed some wired-AND mechanism in this case as well?

7. What is the meaning of using a START BYTE? Could you give me a practical example…

8. Since a START BYTE does not need any acknowledge, how can an error be detected on the transmission of that byte? I suppose that if an error occurs in the START BYTE, the addressed device cannot read its address (that is sent in the byte following the START BYTE) and then cannot send any acknowledge to the master. In this way an occurring error on the START BYTE can be detected. Is my consideration correct?

9. In an Hs mode bus, a master code byte does not need any acknowledge from other devices but actually, after the master code byte is sent, a not-acknowledge bit is always occurring: is that a dummy not-acknowledge? I mean: is that not-acknowledge automatically (implicitly) set by the same device (that has sent the master code byte) simply releasing the SDA line, and then pulling it up?


Thank you for helping me.


Nicola

 

[white_shadow]

Re: I2C-bus questions

1. The arbitration mechanism is well described in specification (version 2.1) given by Philips. However, no information is given in case of arbitration between a transmitter and a receiver master device. I suppose the arbitration is first made on the 7 address bits of slave. In the worst case of addresses equal to each other, the arbitration is wined by the writing master, i.e. 8th bit = LOW. Is it correct?

The 8th bit is for R/W. the 9th bit is for ACK/NACK. If two slaves share the same address the system is designed poorly.

2. Is even the arbitration taking place through the same wired-AND mechanism used by synchronization on SCL line?

The master issues SCLK. Slaves synchronize to it.

3. Is the synchronization process taking place only during the arbitration (and just later the acknowledge bit in order the slave can tell the master to wait before transmitting again as a handshake mechanism)?

Synchronization should only need to take place once, although there probably is finite adjustment.

4. Is the synchronization process continuing until the end of the byte after a master understands it lost arbitration?

Is this a re-phrase of question #3?

5. Is it possible the occurring of two different clock signals with equal frequency and opposite phase during the synchronization process? I suppose it is not, since the SCL line is HIGH when not used yet, and then both the two clock signals begin from HIGH position: they cannot have opposite phases since their phase shifting is at maximum equal to the START condition’s fall time, which is shorter than the minimum SCL clock period.

You answered your own question.

6. If a general call address is sent on the SDA line, every device requiring data from a general call address should reply by sending an acknowledge. How can several devices send acknowledge all together in the slot time of a bit only? As during synchronization process occurs, is it performed some wired-AND mechanism in this case as well?

Only one slave should ACK.

7. What is the meaning of using a START BYTE? Could you give me a practical example…

It is not a START BYTE, but rather a START condition. It is the falling of SDA followed by SCLK.

8. Since a START BYTE does not need any acknowledge, how can an error be detected on the transmission of that byte? I suppose that if an error occurs in the START BYTE, the addressed device cannot read its address (that is sent in the byte following the START BYTE) and then cannot send any acknowledge to the master. In this way an occurring error on the START BYTE can be detected. Is my consideration correct?

Read question #7.

9. In an Hs mode bus, a master code byte does not need any acknowledge from other devices but actually, after the master code byte is sent, a not-acknowledge bit is always occurring: is that a dummy not-acknowledge? I mean: is that not-acknowledge automatically (implicitly) set by the same device (that has sent the master code byte) simply releasing the SDA line, and then pulling it up?

I believe (not sure on this) that every byte transmitted is followed by an ACK. It's a form of error checking. If you write the code properly, you can re-send that data in this case or be aware of transmission failure.