setup violations (reg to memory path)

[subhash_chevella]

Hello friends,

Suppose, memory block is also present in my design.
hence, there is a chance of having a timing path "from reg to memory input" and "memory output to reg".
If I am getting setup violations in this particular timing path.
What should be the first approach I should follow to fix these kind of violations?
How can we fix these kind of violations?

regards,
Subhash

 

[rca]

first, if it is a synchronous memory, your timing is considere as reg to reg, like flop-to-flop, we could say, memory element to memory element.

you need to understand why your path is too long,
do you have the memory on opposite edge, that reduce by two the available time?
check the setup constraints on this particular memory-pin, some have huge setup constraint.

 

[subhash_chevella]

Hello rca,
thanks for the quick reply.

Ya, it is a synchronous memory.

do you have the memory on opposite edge, that reduce by two the available time?

I didn't get the exact meaning of the above sentense?

I verified the setup time for this memory-pin. Its having large setup time of alomost 2ns.
What can I do to fix this?

regards,
Subhash

 

[oratie]

How to fix? You can play with clock skew (between flipflops and mem). For example: If you have positive slack on path reg->mem, you may reduce clock tree length to this mem, so you will get more time for mem->reg path. Another way: some memory compilers allow to compile memory cuts with different output drive strength, maybe there is a huge output load on mem's outputs, by increasing drive strength the mem output transition will be shorter, and the slack will be lesser.

 

[subhash_chevella]

hi oratie,

I am getting the violation in reg-mem path.
I verified the slack for mem-reg path. It is having very low positive slack.
At this situation I can't play with the clock skew, right..?

---------- Post added at 17:33 ---------- Previous post was at 16:58 ----------

Hello,

I also have a path reg-mem which is asynchronous and corresponding mem-reg path which is synchronous.
getting violations in reg-mem path.
I tried to play with clock, but I can't able because, corresponding mem-reg path is having very less positive slack.
What can one do for this kind of situations?
Can't I fix this?

It will be very helpfull for your suggestions.

regards,
Subhash

 

[oratie]

Well, you have very small positive slack in mem_reg path. I assume, it is just after synthesis. Still try to adjust clock length to memory, and see, if synthesis still will be able to keep positive slack in mem_reg path. (it may happens, because, synthesis tool as soon as it get positive slack does not trying to increase this positive slack. it is enough to have non-negative slack ).

Another way: you have problem in reg_mem path. Look at path before this reg (i mean reg->reg->mem). Maybe you can adjust clock not to the mem, but to the reg.

What else: if you have this timing violation after placement - may you shorter wire length in the reg_mem path? (by placing these reg and mem closer)

 

[rca]

Opposite edge, I means fret on rising edge and memory on falling edge of th clock

---------- Post added at 18:24 ---------- Previous post was at 18:23 ----------

Flop on rising edge and mem on falling edge

 

[dll_fpga]

people in this forum have good vision

Hello friends,

Suppose, memory block is also present in my design.
hence, there is a chance of having a timing path "from reg to memory input" and "memory output to reg".
If I am getting setup violations in this particular timing path.
What should be the first approach I should follow to fix these kind of violations?
How can we fix these kind of violations?

regards,
Subhash

 

[sharif.shiek]

Hi, subhash, i think increasing the size of reg in reg-mem path will cause to decrease the setup violations, and one more solution is use lvt cells to improve its switching speed which will cause to decrease the delay...i hope its helpful..

 

[owen_li]

Hi suhash.
Actually, I met the similar situation in my previous project.
What I did is " group path" on these specified timing path. And set a greater weight on this path group.
Then P&R tool will give more focus on the optimization of these paths.
You can take a try. thanks!

 

[dll_fpga]

If it is just after synthesis ....i think we can place the memory and register close together so that the path length is less.....

Hi suhash.
Actually, I met the similar situation in my previous project.
What I did is " group path" on these specified timing path. And set a greater weight on this path group.
Then P&R tool will give more focus on the optimization of these paths.
You can take a try. thanks!