setup violation in slow corner and hold violation in fast corner in the same path

Say you have a setup violation in a slow corner and a hold violation in the fast corner in the same path. How would you approach fixing this?

Interstage delay between registers is too much. Re-register, flatter logic, pipeline, clock pullback are some options (which may or may not play, according to how many and how vigorous an infestation of Methodology Harpies in house).

linlinlin38 said:

Say you have a setup violation in a slow corner and a hold violation in the fast corner in the same path. How would you approach fixing this?

Click to expand...

it is unlikely to have such scenario. The most critical hold path may share some logic with the most critical setup path, but there typically are cells that do not overlap. For the ones that do not overlap, traditional cell sizing optimization still applies.

I've seen it, trying to do a 400MHz main clock in
0.5u CMOS. Only on the setup side, as we designed
for zero hold time in the DFFs and so hold violations
in a uniform clock field can't happen.

But "uniform" is a question, clocking with some other
could bring all kinds of kooky timing events / relations.

This could be an asynchronous design, could be in a
synchronizer / domain-crossing where such things
do happen and "expectations must encompass a
reality"? The OP leaves all that to the reader's
assumptions.

In any case, -if- timing slide is excessive, reducing
delay* between register stages is the only thing I
know, for it.

* that's from a "flop's eye perspective" - games can
be played with local clock, but you'll get very little
love from your local MHs, the customer's or their
customer's.