Setup & Hold -> what's the physical explanation?

Hi All,

What's the physical explanation for the Setup & Hold requirements?

Thank you!

Hi,

You are talking about timing?

Setup time.
For example a D-FF. It has a data input and a clock input. Often you first must apply the data, then th clock edge. Data must be set up before clock edge.

Hold time:
Imagine a three state output buffer. There is an enable pin. When you disable the buffer, then for a short time the buffer is still low impedance before becoming high impedance. This is called hold time.

Klaus

Imagine a three state output buffer. There is an enable pin. When you disable the buffer, then for a short time the buffer is still low impedance before becoming high impedance. This is called hold time.

Click to expand...

Could you explain more please? Don't catch this point...

Actually I was asked in the interview "What's the physical explanation for the Setup and Hold time requirements?" As I understand, they expected to hear about CMOS behavior or internal structure of FlipFlop (or Latch).

Hi,

I just reviewed my statement about "hold time". I was wrong on that. It has nothing to do with three state buffers.

Hold time:
For example a D-FF. It has a data input and a clock input. Often you need to hold the data after the clock edge for a short time.

***
here a datasheet of a D-FF:

You may find the values for setup tim and hold time in a table on page10. Also you may find a timing diagram Figure8 on page11.

***
Again, sorry for the mistake, that eventually confused you.

Klaus

Hi,

A Flip Flop is made up of master latch and a slave latch.

Setup Time: We need to provide enough time for the input capacitance of Master latch to be charged up or discharged down, before the Master latch captures the data. To ensure that this happens ,we have a setup time requirement. If we violate this setup time requirement. We cannot be sure what value will be captured by the master latch, may be 0, may be 1..

Hold time: Even after the Master latch has captured the data, the clock of Master gets disabled and the clock of slave gets enabled, now we should provide Enough time for the master latch to be fully disabled and slave latch fully enabled. If the data at input of Master latch changes and at that instant the clock of master latch had not gone into inactive level, then we might enter into metastability. To ensure this we have a hold check in a flip flop.

ivlsi said:

Actually I was asked in the interview "What's the physical explanation for the Setup and Hold time requirements?" As I understand, they expected to hear about CMOS behavior or internal structure of FlipFlop (or Latch).

Click to expand...

This part of your question makes me more curious.
If I were you, I would have asked the interviewer what is meant by "physical explanation".

If the data at input of Master latch changes and at that instant the clock of master latch had not gone into inactive level, then we might enter into metastability.

Click to expand...

Why? Can you explain physically why a metastability happens?

ivlsi said:

Why? Can you explain physically why a metastability happens?

Click to expand...

It's a race to sample and store data that is changing at the same time (clock edge). The precise relative latency of the device and signals determines if the outcome of the race is guaranteed ( to be late or early) or whether it is uncertain hence called metastable.