Setup/Hold time violation -- Frequency dependancy

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cherukukeshav

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hold time violation

Hi,

Can any body tell me why holdtime violations will not get affected with change in frequency. But setup time violations will depend on the frequency.

Please explain me the relation of setup time/ hold time with frequency.

- Thanks
 

hold time violation example

Think of set up time as being frequency dependent because it has to do with when the data arrives... We can't have the data arrive exactly when the rising edge of destination clock is approaching because it would lead to metastability. This is an important concept when you are crossing clock domains, where one domain is faster or slower than the other. Set up time is always before the rising edge of the destination flop.

Hold time has less to do with when the data arrives and more to do with once it has arrived (after the destination flop's active edge) let it remain steady for some time. The diagram should help you see this.
 
set up and hold time violations

Thanks for the reply,

It would of great help if you explain with a setup and hold violation example, where by changing frequency we can avoid setup violations , whereas the same is not possible with hold violation elimanation.
 

setup hold time

Suppose you have a register to register path with each register clocked by a clock of frequency 10 MHz.Consider a clock edge at time 0 at reg1 and a clock edge at time 0.1us at reg2.The setup check would be between these two edges.But if the frequency varies the time available would be different from 0.1us.But for the hold check which is done for the clock edge at time 0 at reg2,even if the frequency changes, the hold check would still be at time 0.So frequency of the clock has an effect only on the setup and not the hold

Thanks,
jean
 
setup time frequency relation

hello friend,

It is already described by me clearly in the following post.




cheers..

SunilB
asic-dft.com
 
I understand that in order not to violate setup time (tsu) of a flip flop, the clock frequency must not exceed a certain limit, i.e. there is a maximum frequency, Fmax. However, when refering to the external setup time (TSU) of a chip (i.e. the chip's external data and clock pin setup time), does the Fmax varies according to the setup time provided? Example: if TSU=5ns, Fmax=100MHz; TSU=8ns, Fmax=120MHz. Is this true?
 

Which one is critical for estimating maximum clock frequency of a circuit, setup time or hold time
thanks in advance
 

Set up time is enough to determine the max operating frequency...
Max operating frequency is where the setup slack is zero for the critical path....
as the hold violation is frequency independent...

please someone correct me if i am wrong.....

BISH said:
Which one is critical for estimating maximum clock frequency of a circuit, setup time or hold time
thanks in advance
Click to expand...
 
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    BISH

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BISH said:
Which one is critical for estimating maximum clock frequency of a circuit, setup time or hold time
thanks in advance
Click to expand...

quick answer, SETUP time. For detail visit the link mentioned in previous post.

Hope this will be helpful.
 

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