noco3148
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Hi all,
I'm using Design Compiler for synthesis my verilog code.
When I synthesis my code without clock-gating, there is no timing violation in synthesis report and post-synthesis simulation with VCS.
And then I re-synthesis with -gate_clock option to compile_ultra commands and the synthesis report says no timing violation occurs.
But VCS says there are many setup and hold violation in my synthesis result.
Furthermore, the gate count of my synthesis result is also decreased...
I think I made a mistake in my synthesis, but I don't know how to fix it.
Please help me.
I'm using Design Compiler for synthesis my verilog code.
When I synthesis my code without clock-gating, there is no timing violation in synthesis report and post-synthesis simulation with VCS.
And then I re-synthesis with -gate_clock option to compile_ultra commands and the synthesis report says no timing violation occurs.
But VCS says there are many setup and hold violation in my synthesis result.
Furthermore, the gate count of my synthesis result is also decreased...
I think I made a mistake in my synthesis, but I don't know how to fix it.
Please help me.