Setup/Hold scenario when pos edge launch flipflop - neg edge capture flipflop

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nandithaa_m

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Can anyone help me prove why there will not be any hold violations if launch ff is pos-edge and capture ff is neg-edge ?
Also, can you help me understand setup scenario also ?
 

nandithaa_m said:
Can anyone help me prove why there will not be any hold violations if launch ff is pos-edge and capture ff is neg-edge ?
Click to expand...

That means you are defining Negative edged FF. Why there will not be Hold Violations?.

Hold violations will be there.

Set up time is min time from D-Clk so that the data is stable.
Hold time is min time from Clk-D so that the data is stable.

Hope this helps.

- - - Updated - - -

Attached are good articles on Set up and Hold time.
 

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  • setup1_1210.pdf
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  • timing_1261.pdf
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Hello,

We are checking hold violation on the same clock cycle...and now as per your scenario,launch ff is +ve edge and capture ff is -ve edge...so you already providing the half cycle delay....so there is very less chances for the hold violation...

Thanks & Regards,
Maulin Sheth
 

maulin sheth said:
Hello,

We are checking hold violation on the same clock cycle...and now as per your scenario,launch ff is +ve edge and capture ff is -ve edge...so you already providing the half cycle delay....
Click to expand...

Why there is less chance of Hold time Violations.

I agree that hold time is measured at one clock edge(cycle).

Whether is Lauch or latch??.. Both you used same terminology.
 

Prashanthanilm said:
Why there is less chance of Hold time Violations.

I agree that hold time is measured at one clock edge(cycle).

Whether is Lauch or latch??.. Both you used same terminology.
Click to expand...

Because we are providing half cycle delay...so in this half cycle ,the hold violation is solved...
 

Actually I am not getting the concept of Half Cycle delay.
Please Elaborate it.

One more thing;
So, you mean Positive edged FF is not providing Half Cycle delay???
 

Half cycle delay is time between the +ve edge and the -ve edge....
I am not getting your question : So, you mean Positive edged FF is not providing Half Cycle delay???
 

The Question was " why there will not be any hold violations if launch ff is pos-edge and capture ff is neg-edge ?" ( I think it is latch instead of launch)

The above statement corresponds to Negative or Positive triggered FF?

So, whether the half cycle delay favours both the triggered FF?
 

No it's not latch..its a triggered FF...
Yea above statements are corresponding to Negative or Positive triggered FF.
Yea It will support for both the triggered FF..but not always..for that we just need to do the timing analysis for particular situation and mostly depends on the skew....
Pl correct me if any misunderstanding by me..
 

Yes, Exactly . The set up time and Hold time depends upon the delay bt Clk to q, combinational delay and so. Set up time also depends upon operating freq, whereas Hold time does not depend upon freq.

The Question was " why there will not be any hold violations if launch ff is pos-edge and capture ff is neg-edge ?"

I believe that there are HOLD violations in any triggered FF.

I think I misunderstood your statement "so there is very less chances for the hold violation"-->Acc to me, it is not less chance. It has to be fix. Hold violations are not so rare.

So, there are both Set up and Hold violations in FF.(And I dont think any one of them has less chance)

Correct me, if I am wrong.
 

hi Guys,

Nice discussion. Actually when you say Hold violation, it means the same clk cycle will be verified. And here you are launching in +ve edge and you are capturing in -ve edge, but the hold check will be done wrt to 2 +ve clk cycles and hence we arrive at a half cycle additional margin, which hold value cannot cross. Hence Hold willnot occur in case of half cycle path.
 

Yea..hold violation is occur in any triggered FF....but in this case scenario is that,launch ff is triggered at the +ve edge and capture ff is -ve edge triggered...if we considered only 2 ffs with this scenario than there is no chance for the hold violation...
 
Thanks Maulin and Sakthik.

Doubts:
1."here you are launching in +ve edge and you are capturing in -ve edge"

I am not familiar with the word launch i suppose. So, whether the above is Positive triggered FF or Negative Triggered FF.

2.I think I am confused with some other architecture...if we considered only 2 ffs with this scenario than there is no chance for the hold violation...

Can you guys please update the schematic of this.

I am not getting how this avoids Hold Violation.
 


Hello,
I have attached one image...so just check it..it will clear that what launch and capture word mean in STA.
 

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  • Launch_Capture_FF.ppt
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Hi Guys,

Thanks for the response. The hold violation case matches my assumptions. This is the equation that I have for setup. Looks like there is less chance of set-up in this scenario.
I derived setup equation based on the schematic posted above.
[T(launch)+T(clock2Q)+T(comb)]-[{T(cycle)/2}+T(capture)] > T(setup)

In normal case, where launch and capture flip-flop are both pos-edge or neg-edge, the setup equation looks like this.
[T(launch)+T(clock2Q)+T(comb)]-[T(cycle)+T(capture)] > T(setup)

So, in this special scenario, Tcycle is Half, which means it should be able to easily meet setup also ??

But if you think clear, Time Period is half, freq is doubled. Setup should gets worse. Can some one explain me this scenario ?
 

Waw!! Thank you Maulin.

Actually, I was not familiar with terms Launch and Capture. Now its clear.

By, Acc to the Lauch and Capture FF,

Hold Violations happen: if Tholdcap < TFFlaunch + Tpropogation - Tskew.

Correct me if I am wrong.

Or can you prove me with some thing , that Hold violations will be ignored or won't happen.

Any Help would be really appreciated.

Thanks again.
 

Hi Guys,

Thanks for the response. The hold violation case matches my assumptions. This is the equation that I have for setup. Looks like there is less chance of set-up in this scenario.
I derived setup equation based on the schematic posted above.
[T(launch)+T(clock2Q)+T(comb)]-[{T(cycle)/2}+T(capture)] > T(setup)

In normal case, where launch and capture flip-flop are both pos-edge or neg-edge, the setup equation looks like this.
[T(launch)+T(clock2Q)+T(comb)]-[T(cycle)+T(capture)] > T(setup)

So, in this special scenario, Tcycle is Half, which means it should be able to easily meet setup also ??

But if you think clear, Time Period is half, freq is doubled. Setup should gets worse. Can some one explain me this scenario ?
 

nandithaa_m said:
Hi Guys,


So, in this special scenario, Tcycle is Half, which means it should be able to easily meet setup also ??

But if you think clear, Time Period is half, freq is doubled. Setup should gets worse. Can some one explain me this scenario ?
Click to expand...

Hello,
I dont think so that the tcycle is half..we are not changing the time period or frequency....we are just passing the inverted clocks....so it doesn't effect the frequency of time perid..

We mostly worried about the hold time...and not that much worry for setup violation as it is depends on the frequency while hold time is not dependent on the frequency.....so we can solve setup violation by just changing the frequency..
 

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