Hi,
I have a question related to the setup and hold timing violation. I'm curious why at place optimization stage , there are setup and hold timing violation even though the clock network is ideal?
from your question I gather that you do not understand what is meant by an ideal clock.
It means the clock arrives at all flip-flops at the same time, we can say at time t=0. There is no jitter, no skew, no insertion delay. With this information in mind, it is easy to understand how setup can still be violated... and so can hold.
It's a data problem, not a clock problem. Some path(s)
with too many logic stages between clocked FFs. That
is what eats setup time.
It's difficult to get a hold time violation with a common
clock, 'flop delay ought to exceed any front end hold
requirement. If you do have actual hold time violations
that would be "interesting" (more likely with mis-phased
external signals than anything generated intra-clock-
domain).
from your question I gather that you do not understand what is meant by an ideal clock.
It means the clock arrives at all flip-flops at the same time, we can say at time t=0. There is no jitter, no skew, no insertion delay. With this information in mind, it is easy to understand how setup can still be violated... and so can hold.