setup and hold time in CPLD's

somebody can explain to me the benefit of 0 (zero) or negative hold time in CPLD's

I was told that max2 has positive hold time and that is bad, but I don't understand why.

setup time is before clock edge, hold time is after the clk edge, right?

Ahhh .. the good old Tsetup and Thold .... this two parameters are Sequential parameters in EPLD,PALS.GALS .. they are OBLIGATORY to be respected ..
Tsetup is the time necessary (min) of a signal to be LATCHED by the clock ..
Otherwise the clock won't see it .. If this signal is smaller than required .. Its FRONT will still be PROPAGATING and won't arrive when the clock does it .
Thold is another critical time is the (min) amount of time necessary to BE PRESENT
so WHEN the CLOCK has switched ..the CIRCUIT is STABLE and REMAINS stable .

VERY FAST CIRCUITS have a very small Tsp and Thd requirements .. But they will alwasy be > 0 .. Zero is a FILOSOFICAL VALUE .. negative means that it won't make it .. 0 will always means pico seconds ... an electron jumping from one atom to another it will still require time .. IN ELECTRONICS tsetup or thld ZERO is considered so small that the CLOCK is so SLOW to be CONSIDERED .

Yes, but the device has itself atrributes, if the Th is a negative value, that means it need more short time to hold.

So if I understand you well, if a timing report gives a Th of -5.05ns, this means that that FF is unsensitive for the toggling of the clock. A positive value will slow down the system, right?