thanks for the comment but the options also not worked for me. While running optDesign there was only less number of instances are added and deleted so that i think I am not getting any improvement in timing.
So I think I should use some other options. and I dont Know which are the best methods to use to resolve the fore mentioned problem.
I think the nets are fixed but I don't know exactly. Do you think I have to run ECO again.
You have to deal with them separately. The standard practice in ASIC/SoC designing is to fix all setup violations before the PnR stage and let the layout engineers fix the hold violations during the PnR stage.
According to the error you are currently having, go back to the relevant development flow stage and fix the problems.
Actually I already fixed the timing till POST CTS stage. After that I did nanoRoute. then when I gave timeDesign -postRoute command I got these timing violations.
So I am in the middle of nowhere to spot the reason. Anyway I am checking from first. But I think there must something I am missing.